Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors

A semiconductor package assembly, comprising:

• a first semiconductor package including:
• a substrate including an upper surface;
• and
• a package body disposed adjacent to the substrate, the package body including an upper surface and defining openings disposed adjacent to the upper surface of the package body;
• wherein the openings are configured to at least partially expose conductive bumps extending vertically from the substrate such that each of the conductive bumps includes an uncovered portion and a covered portion separated at a boundary adjacent to the each of the conductive bumps;
• and
• wherein the openings have:
• a peripheral depth extending from the upper surface of the package body to the boundary adjacent to the each of the conductive bumps;
• and
• a central depth extending from the upper surface of the package body to an upper end of the each of the conductive bumps;
• and
• wherein the peripheral depth is in the range of 1.5 to 4.5 times as large as the central depth.

A semiconductor package, comprising:

• a substrate having an upper surface;
• conductive connectors extending upwardly from the upper surface of the substrate, at least one of the conductive connectors having a first width;
• and
• a package body disposed adjacent to the substrate and having an upper surface, the package body defining cavities each having a lateral surface circumscribing a corresponding one of the conductive connectors, each of the cavities at least partially exposing the corresponding one of the conductive connectors;
• wherein at least one of the cavities has a second width adjacent to the upper surface of the package body, the second width being at least as large as the first width;
• and
• wherein the cavities partially expose the conductive connectors to define covered portions and uncovered portions of the conductive connectors, at least one of the cavities defines a boundary between a covered portion and an uncovered portion of a respective one of the conductive connectors, the respective one of the conductive connectors has an upper end, and the boundary is closer to the substrate than to the upper end of the respective one of the conductive connectors.