Variable feature interface that induces a balanced stress to prevent thin die warpage
AssigneeQUALCOMM Incorporated
InventorsArvind Chandrasekaran, Ratibor Radojcic
Life of this patent
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Abstract
A packaged semiconductor product includes a packaging substrate coupled to a semiconductor die through an interconnect structure with elements of variable features. The interconnect structure may be bumps or pillars. The variable features of the interconnect structure induce a reverse bend on the semiconductor die that mitigates warpage of the semiconductor die during semiconductor assembly by balancing bending of the packaging substrate during reflow. The variable features can be variable height and/or variable composition.
Claims20
A semiconductor die, comprising an interconnect structure with at least one variable feature inducing an inverse bend on the semiconductor die.
A semiconductor die comprising:
- an interconnect structure with at least one variable feature inducing an inverse bend on the semiconductor die, the inverse bend counteracting bending during semiconductor assembly;
- and
- a second packaging substrate coupled to the first packaging substrate through a second interconnect structure comprising elements of variable features that induces opposite bending on the second packaging substrate to mitigate warpage after semiconductor assembly.
A method of semiconductor assembly, the method comprising:
- providing on a semiconductor die an interconnect structure with at least one variable feature that induces a reverse bend on the semiconductor die during the semiconductor assembly;
- and
- coupling the semiconductor die to a packaging substrate through the interconnect structure.
A method of semiconductor assembly, the method comprising:
- providing on a semiconductor die an interconnect structure at least one variable feature that induces a reverse bend on the semiconductor die during the semiconductor assembly;
- coupling the semiconductor die to a packaging substrate through the interconnect structure;
- and
- applying a temperature to reflow the interconnect structure that causes the packaging substrate to bend an amount approximately equal to the reverse bend on the semiconductor die, in which applying the temperature further comprises applying a first temperature at a center of the interface structure and applying a second temperature at a periphery of the interface structure.
A semiconductor system, comprising:
- a packaging substrate,
- a semiconductor die coupled to the packaging substrate through means for communicating with the packaging substrate having elements of at least one variable feature that induces a reverse bend on the semiconductor die to mitigate warpage of the semiconductor die during semiconductor assembly.
Dependencies are inferred from the claim text.