Wafer structure
AssigneeMacronix International Co., Ltd.
InventorChin-Cheng Yang
Life of this patent
Estimating the term…
Abstract
A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark.
Claims8
A wafer structure comprising:
- a plurality of dies, each of the dies having an integrated circuit formed thereon, wherein the circuit includes an upmost metal layer that includes bonding pads;
- an edge portion where a composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed, wherein a cavity is formed in the composite dielectric layer over the edge portion;
- a passivation layer over the whole wafer, covering the upmost metal layer;
- and
- a UV-blocking metal layer on the passivation layer, covering the edge portion and at least a portion of each of the dies, wherein the cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark.
Dependencies are inferred from the claim text.