Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

A semiconductor product comprising:

• a semiconductor substrate having a top surface and a bottom surface
• a semiconductor chip formed including said substrate,
• said semiconductor chip having a Front End Of Line (FEOL) layer with an upper surface formed above said top surface and having a Back End Of Line (BEOL) layer including therein an interconnection structure formed above said upper surface;
• said semiconductor chip and said interconnection structure having a perimeter;
• a barrier edge selected from the group consisting of a crackstop barrier and a perimeter with a diced edge on said perimeter;
• and
• a trench cut into said semiconductor chip between said diced edge and said barrier edge.

A semiconductor product comprising:

• said semiconductor product having a top surface and a bottom surface including a semiconductor chip;
• said semiconductor product having an upper surface and a perimeter, with a crack stop barrier formed in said chip within said perimeter, and with an active device Front End Of Line (FEOL) layer and a Back End Of Line (BEOL) layer above said FEOL layer with said BEOL layer including an interconnection structure with said FEOL and BEOL layers formed above said top surface of said substrate;
• a barrier formed in said chip within said perimeter;
• a trench cut extending down through said upper surface of said semiconductor product between said perimeter and said barrier but extending only partially down into said active device FEOL layer or said substrate between said crack stop barrier and the outermost of said perimeter;
• and
• a blanket underfill layer over said product completely covering said interconnection structure and completely filling said trench.