US 8,076,734 B2Granted

Semiconductor structure including self-aligned deposited gate dielectric

AssigneeInternational Business Machines Corporation

InventorHuilong Zhu

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor structure, such as a field effect device structure, and more particularly a CMOS structure, includes a gate dielectric that is at least in-part aligned to an active region of a semiconductor substrate over which is located the gate dielectric. The gate dielectric comprises other than a thermal processing product of the semiconductor substrate. In particular, the gate dielectric may be formed using an area selective deposition method such as but not limited to an area selective atomic layer deposition method. Within the context of a CMOS structure, the invention provides particular advantage insofar as the use of a self-aligned method for forming a gate dielectric aligned upon an active region of a semiconductor substrate may avoid a masking process that may otherwise be needed to strip portions of an area non-selective blanket gate dielectric.

Claims17

Dependent claims

A semiconductor structure comprising:

a semiconductor substrate including an isolation region that surrounds an active region;
a gate dielectric comprising other than a thermal processing product of the semiconductor substrate located on a surface of the active region of the semiconductor substrate;
a gate electrode located on a surface of said gate dielectric;
and
a pair of source and drain regions located within the active region and separated by a channel region located beneath the gate electrode, wherein said gate dielectric has a first set of edges in a first direction and a second set of edges in a second direction that intersects said first direction, wherein said first set of edges in said first direction is aligned to, and does not extend beyond, outer edges of said gate electrode, and said second set of edges in said second direction has a first edge that coincides with, and is aligned to, and does not extend beyond, a first edge of said isolation region in a view in a direction perpendicular to said surface of said active region and a second edge that extends beyond a second edge of said isolation region.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/946,942Filed 29 Nov 2007
Published: US 2009/0140345 A14 Jun 2009
Granted: 13 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 64/691
Characterised by the insulator, e.g. by the gate insulator: comprising metallic compounds, e.g. metal oxides or metal silicates
H10D 84/0177
Manufacturing their gate conductors: the gate conductors having different materials or different implants
H10D 84/0181
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate insulating layers