US 8,076,730 B2 · Transistor level routing

Abstract

System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area. The electrical connection includes a high-k dielectric layer and a metal layer but not a poly-silicon layer and the metal layer is arranged directly over the high-k dielectric layer.

Claims22

Dependent claims

A semiconductor device, the semiconductor device comprising:

a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first semiconductive layer;
a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second semiconductive layer;
and
an electrical connection connecting the first semiconductor device with the second semiconductor device and overlying the first active area, the second active area and a portion of the substrate between the first active area and the second active area, wherein the electrical connection comprises a third high-k dielectric layer and a third metal layer but not a semiconductive layer and wherein the third metal layer is arranged directly over the third high-k dielectric layer.

1 more element

Dependencies are inferred from the claim text.

Transistor level routing

Life of this patent

Transistor level routing

Life of this patent

Abstract

Claims22