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US 8,076,717 B2Granted
Vertically-oriented semiconductor selection device for cross-point array memory
AssigneeMicron Technology, Inc.
InventorsGurtej Sandhu, Chandra Mouli, John K. Zahurak
Life of this patent
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Abstract
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
Claims19
A transistor comprising:
- a semiconductor material base;
- a semiconductor material mesa upstanding from said base;
- a first silicide on an upper surface of said mesa;
- a second silicide supported on said base and abutting against at least a first side of said mesa for supplying an electrical connection to said mesa;
- first and second regions respectively coupled to the first and second silicide, the first and second regions being doped to a first type and one or more channel regions between the first and second regions being doped to a second type;
- and
- a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first gate structure being operative to control current flow in said channel regions between said first and second silicides through said mesa.
4 more elements
A transistor comprising:
- a semiconductor material base;
- at least one linearly extending semiconductor mesa structure, upstanding from said base;
- at least one first silicide material element extending along an upper level of each mesa structure in said linear direction;
- a second silicide material element on said semiconductor material base abutting against at least a first side of said at least one linear extending mesa structure for providing an electrical connection to said mesa structure;
- and
- a first mesa sidewall gate structure provided on said first side of said mesa structure and comprising a gate insulator material and an overlying gate conductor, said first gate structure being operative to control current flow between said first and second silicide material elements through said mesa structure.
3 more elements
A memory array comprising:
- a semiconductor material base;
- a plurality of linearly extending semiconductor mesas upstanding from said base, spaced from one another and arranged in parallel;
- a plurality of first silicide elements respectively extending along an upper level of each of said mesas in said linear direction;
- a plurality of second silicide elements respectively on said base at least at a first side of each mesa structure;
- a plurality of first mesa sidewall gate structures respectively provided on said first side of each of said linearly extending mesa and each comprising a gate insulator material and an overlying gate conductor, first gate structures being operative to control current flow between said respective first and second silicide elements through said respective mesa structure;
- a plurality of memory cells, each electrically coupled via a first side of said memory cell to one of said first silicide elements;
- and
- a plurality of conductive lines arranged so that each of said memory cells is electrically coupled via a second side of said memory cell to one of said conductive lines so that no two memory cells are electrically coupled to the same first silicide element and the same conductive line.
5 more elements
A memory array comprising:
- a semiconductor material base;
- a plurality of semiconductor mesa structures, upstanding from said base, spaced from one another within one or more lines of mesa structures;
- a plurality of first silicide elements respectively extending along an upper level of each of said mesa structures;
- a plurality of connected second silicide elements respectively supported on said semiconductor material base at least at a first side of each mesa structure for providing an electrical connection to said respective mesa structures;
- a plurality of first mesa sidewall gate structures respectively provided on said first side of each of said mesas and extending linearly so that a gap between each of said mesa structures in a line is spanned by said gate structure, each gate structure comprising a gate insulator material and an overlying gate conductor, said first gate structures being operative to control current flow between said respective first and second silicide elements through said respective mesa structure;
- a plurality of memory cells, each electrically coupled via a first side of said memory cell to a respective one of said first silicide elements;
- and
- a plurality of conductive lines arranged so that each of said memory cells is electrically coupled via a second side to one of said conductive lines so that no two memory cells are electrically coupled to the same first silicide material element and the same conductive line.
5 more elements
Dependencies are inferred from the claim text.