Non-volatile memory devices having a multi-layered charge storage layer

A non-volatile memory device, comprising:

• a substrate having a first cell region, a second cell region connected to one side of the first cell region, and a high-voltage region;
• a cell gate electrode placed on the first cell region;
• a multi-layered charge storage layer interposed between the cell gate electrode and the substrate and comprising a tunnel insulation layer, a trap insulation layer, and a blocking insulation layer;
• a selection gate electrode placed on the second cell region and comprising a lower selection gate and an upper selection gate connected to an upper region of the lower selection gate;
• a residual multi-layered pattern interposed between a part of an upper surface of the lower selection gate and the upper selection gate, the residual multi-layered pattern comprising a same material as that interposed between the cell gate electrode and the substrate;
• a selection gate insulation layer interposed between the selection gate electrode and the substrate;
• a high-voltage gate electrode placed on the high-voltage region and comprising a lower high-voltage gate and an upper high-voltage gate, which are stacked sequentially;
• and
• a high-voltage gate electrode insulation layer interposed between the high-voltage gate electrode and the substrate and having a thickness greater than a thickness of the selection gate insulation layer;
• wherein the lower selection gate and the lower high-voltage gate comprise a same material, and
• wherein the cell gate electrode, the upper gate selection gate, and the upper high-voltage gate comprise a same material.

A non-volatile memory device, comprising:

• a substrate having a first region and a second region;
• a first gate electrode crossing over a first active region in the first region;
• a multi-layered charge storage layer interposed between the first gate electrode and the first active region, the multi-layered charge storage comprising a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked;
• a second gate electrode crossing over a second active region in the second region, the second gate electrode comprising a lower gate and an upper gate connected to a region of an upper surface of the lower gate;
• a gate insulation layer interposed between the second gate electrode and the second active region;
• wherein the first gate electrode and the upper gate of the second gate electrode comprise a same material;
• and
• a residual multi-layered pattern interposed between a part of an upper surface of the lower gate of the second gate electrode and the upper gate of the second gate electrode;
• wherein the residual multi-layered pattern comprises a same material as that interposed between the first gate electrode and the substrate.