US 8,076,710 B2Granted

Semiconductor device and method for manufacturing the same

AssigneeFujitsu Semiconductor Limited

InventorHiroki Sugawara

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Abstract

A method for manufacturing a semiconductor device is provided. The method includes forming multiple conductive patterns 13a, forming an intermediate insulating film 16 on all of device isolation insulating films 6 and the conductive patterns 13a, forming a second conductive film 17 on the intermediate insulating film 16, patterning the second conductive film 17, the intermediate insulating film 16, and the multiple conductive patterns 13a, individually, to make the conductive patterns 13a into floating gates 13c and to make the second conductive film 17 into multiple strip-like control gates 17a. In the method, an edge, in a plan layout, of at least one of each of the conductive patterns 13a and each of the device isolation insulating films 6 is bent in a region between the control gates 17a adjacent in a row direction.

Claims22

Dependent claims

A semiconductor device comprising:

a semiconductor substrate;
device isolation insulating films formed in the semiconductor substrate and extending in a row direction;
a tunnel insulating film formed over the semiconductor device between the device isolation insulating films;
a plurality of floating gates formed in a matrix form over the tunnel insulating film;
an intermediate insulating film formed over the floating gates;
and
a plurality of strip-shaped control gates that are respectively formed over the intermediate insulating films and that respectively extend in a column direction, the control gate collectively covering the plurality of the floating gates aligned in a single column, wherein
a residue of the intermediate insulating film is formed to linearly extend over the device isolation insulating film or over the tunnel insulating film in a region between the control gates adjacent in the row direction,
and a portion of the residue is located out of a slanting surface of the device isolation insulating film, and
wherein the residue extends to bend toward an inner side in the column direction of the device isolation insulating film in a plan view, and
the portion of the residue is formed over a top surface of the device isolation insulating film.

8 more elements

A semiconductor device comprising:

a semiconductor substrate;
device isolation insulating films formed in the semiconductor substrate and extending in a row direction;
a tunnel insulating film formed over the semiconductor device between the device isolation insulating films;
a plurality of floating gates formed in a matrix form over the tunnel insulating film;
an intermediate insulating film formed over the floating gates;
and
a plurality of strip-shaped control gates that are respectively formed over the intermediate insulating films and that respectively extend in a column direction, the control gate collectively covering the plurality of the floating gates aligned in a single column, wherein
a residue of the intermediate insulating film is formed to linearly extend over the device isolation insulating film or over the tunnel insulating film in a region between the control gates adjacent in the row direction,
and a portion of the residue is located out of a slanting surface of the device isolation insulating film, and
wherein the device isolation insulating film has a concave portion in the region between the control gates adjacent in the row direction, the concave portion being recessed toward an inner side in the column direction of the device isolation insulating film in a plan view, and
the portion of the residue is formed either over the tunnel insulating film beside the concave portion or over a top surface of the device isolation insulating film.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/542,274Filed 17 Aug 2009 · continuation
Priority: 20 Mar 2007
Published: US 2009/0302368 A110 Dec 2009
Granted: 13 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates