US 8,076,709 B2Granted

Nonvolatile semiconductor memory device

AssigneeRenesas Electronics Corporation

InventorsTetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura

Life of this patent

Estimating the term…

Loading patent…

Abstract

In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Claims20

Dependent claims

A nonvolatile semiconductor memory device comprising:

an array of a plurality of memory cells, each of the memory cells including:
(a) a first semiconductor region and a second semiconductor region, which are formed in a semiconductor substrate;
(b) a first conductor and a second conductor, which are formed over the semiconductor substrate between the first semiconductor region and the second semiconductor region;
(c) a first insulator formed between the first conductor and the semiconductor substrate;
and
(d) a second insulator, which is formed between the second conductor and the semiconductor substrate and provided with an internal charge storage section,
(e) wherein a plurality of first lines and second lines are included, each first line connecting the first conductors of memory cells arranged in a first direction, and each second line connecting the first semiconductor regions positioned on the first conductor side of memory cells arranged in a second direction, which is perpendicular to the first direction,
(f) wherein an erase operation is performed by injecting first carriers, which have a first polarity that is either positive or negative and are generated by band-to-band tunneling, into the charge storage section of a selected memory cell while a potential having the first polarity is applied to the first line that is connected to the selected memory cell, and
wherein, when the first-carrier injection is performed, second carriers, which flow between the first and second semiconductor regions of the selected memory cell and have a second polarity that is opposite the first polarity, are injected into the charge storage section of the selected memory cell.

6 more elements

A nonvolatile semiconductor memory device comprising:

an array of a plurality of memory cells, each of the memory cells including:
(a) a first semiconductor region and a second semiconductor region, which are formed in a semiconductor substrate;
(b) a first conductor and a second conductor, which are formed over the semiconductor substrate between the first semiconductor region and the second semiconductor region;
(c) a first insulator formed between the first conductor and the semiconductor substrate;
and
(d) a second insulator, which is formed between the second conductor and the semiconductor substrate and provided with an internal charge storage section,
(e) wherein a plurality of first lines, second lines, and third lines are included, each first line connecting the first conductors of memory cells arranged in a first direction, each second line connecting the second semiconductor regions positioned on the second conductor side of memory cells arranged in a second direction, which is perpendicular to the first direction, and each third line connecting the first semiconductor regions of the memory cells arranged in the first direction,
(f) wherein an erase operation is performed by injecting first carriers, which have a first polarity that is either positive or negative and are generated by band-to-band tunneling, into the charge storage section of a selected memory cell while a potential having the first polarity is applied to the first line that is connected to the selected memory cell, and
wherein, when the first-carrier injection is performed, second carriers, which flow between the first and second semiconductor regions of the selected memory cell and have a second polarity that is opposite the first polarity, are injected into the charge storage section of the selected memory cell.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/873,679Filed 1 Sep 2010 · division
Priority: JP 2004-10685031 Mar 2004
Published: US 2010/0322013 A123 Dec 2010
Granted: 13 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors
H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 64/037
Of data-storage electrodes: comprising charge-trapping insulators

Family

Application11/030,900Parent of this division · filed 10 Jan 2005
US 2010/0322013 A1Pre-grant publication · published 23 Dec 2010
US 7,847,331 B2Parent of this division
US 2005/0230736 A1Published application
US 8,076,709 B2This patent

From the US filing history. Foreign family members aren’t listed.