Transistor and method for operating the same
AssigneePanasonic Corporation
InventorsDaisuke Ueda, Tsuyoshi Tanaka, Yasuhiro Uemoto, Tetsuzo Ueda, Manabu Yanagihara, Masahiro Hikita, Hiroaki Ueno
Life of this patent
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Abstract
In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.
Claims5
A transistor comprising:
- a Si substrate;
- an underlying layer provided on the Si substrate;
- a first semiconductor layer provided on the underlying layer and having a smaller band gap than the underlying layer, and containing a channel region;
- a second semiconductor layer provided on or above the channel region and having a larger band gap than the channel region;
- a control region provided inside, on, or above the second semiconductor layer and having a p-type conductivity;
- a gate electrode provided in contact with a portion of the control region;
- and a source electrode and a drain electrode provided beside both sides of the control region, respectively,
- wherein the gate electrode is forward biased with respect to the source electrode to inject holes into the channel region, thereby controlling a current flowing between the source electrode and the drain electrode,
- the underlying layer, the first semiconductor layer, the second semiconductor layer, and the control region are each made of a semiconductor compound containing nitrogen, and
- a total impurity concentration of the control region is larger than a concentration of two dimensional electron gas, with no bias voltage applied to the gate electrode, generated in the heterojunction interface between the first semiconductor layer and the second semiconductor layer.
A method for operating a transistor which comprises:
- a Si substrate;
- an underlying layer provided on the Si substrate;
- a first semiconductor layer provided on the underlying layer and having a smaller band gap than the underlying layer, and containing a channel region;
- a second semiconductor layer provided on or above the channel region and having a larger band gap than the channel region;
- a control region provided inside, on, or above the second semiconductor layer and having a p-type conductivity;
- a gate electrode provided in contact with a portion of the control region;
- and a source electrode and a drain electrode provided beside both sides of the control region, respectively,
- wherein the method includes the step of injecting holes from the control region or the second semiconductor layer into the channel region, thereby controlling a current flowing between the source and drain electrodes through the channel region, the underlying layer, the first semiconductor layer, the second semiconductor layer, and the control region are each made of a semiconductor compound containing nitrogen, and
- a total impurity concentration of the control region is larger than a concentration of charge, with no bias voltage applied to the gate electrode, generated in the heterojunction interface between the first semiconductor layer and the second semiconductor layer.
Dependencies are inferred from the claim text.