Fabrication method of pixel structure and thin film transistor
AssigneeAu Optronics Corporation
InventorChin-Kuo Ting
Life of this patent
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Abstract
A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer beside the patterned polysilicon layer forms a source and a drain. A gate insulation layer is formed on the substrate to cover the source, the drain and the patterned polysilicon layer. A gate is formed on the gate insulation layer over the patterned polysilicon layer.
Claims14
A method for fabricating a thin film transistor, comprising:
- providing a substrate;
- forming a patterned polysilicon layer on the substrate;
- forming a metal layer over the patterned polysilicon layer and the substrate;
- removing a portion of the metal layer while retaining a portion of the metal layer on the respective sides of the patterned polysilicon layer to form a source and a drain;
- forming a gate insulation layer over the substrate to cover the source, the drain and the patterned polysilicon layer;
- forming a gate on the gate insulation layer;
- forming a first dielectric layer over the substrate to cover the gate insulation layer and the gate;
- forming a first contact opening and a second contact opening in the first dielectric layer and the gate insulation layer to expose the source and the drain respectively;
- and
- forming a first metal contact layer and a second metal contact layer over the first dielectric layer to fill the first contact opening and the second contact opening and connect electrically with the source and the drain respectively.
A method of fabricating a pixel structure, comprising:
- providing a substrate;
- forming a patterned polysilicon layer on the substrate;
- forming a metal layer over the patterned polysilicon layer and the substrate;
- removing a portion of the metal layer while retaining a portion of the metal layer on the respective sides of the patterned polysilicon layer to form a source, a drain and a data line electrically connected to the source;
- forming a gate insulation layer over the substrate to cover the data line, the source, the drain and the patterned polysilicon layer;
- forming a gate and a scan line electrically connected to the gate on the gate insulation layer;
- forming a dielectric layer over the substrate to cover the gate and the scan line;
- and
- forming a pixel electrode on the dielectric layer, wherein the pixel electrode is electrically connected with the drain.
Dependencies are inferred from the claim text.