Methods and apparatus for thinning, testing and singulating a semiconductor wafer
AssigneeAdvanced Inquiry Systems, Inc.
InventorMorgan T. Johnson
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AssigneeAdvanced Inquiry Systems, Inc.
InventorMorgan T. Johnson
Estimating the term…
A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.
A method, comprising:
A method, comprising:
Dependencies are inferred from the claim text.
The present invention relates generally to semiconductor test equipment, and more particularly relates to methods and apparatus for providing electrical pathways between the pads of integrated circuits on a wafer and circuitry external to the wafer.
Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
As is well-known, integrated circuits are typically manufactured in batches, and these batches usually contain a plurality of semiconductor wafers within and upon which integrated circuits are formed through a variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, and so on.
FIG. 1 is a cross-sectional representation of a silicon-core wafer translator.
FIG. 2 is a cross-sectional representation of a silicon-core wafer translator placed inquiry-side down on a temperature controlled vacuum chuck.
FIG. 3 is a cross-sectional representation of a silicon-core wafer translator placed inquiry-side down on a temperature controlled vacuum chuck and having a layer of wafer bonding thermo-set plastic on the wafer-side thereof.
Reference herein to “one embodiment”, “an embodiment”, or similar formulations, means that a particular feature, structure, operation, or characteristic described in connection with the embodiment, is included in at least one embodiment of the present invention. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.
Terminology
Pad refers to a metallized region of the surface of an integrated circuit, which is used to form a physical connection terminal for communicating signals to and/or from the integrated circuit.
From the US filing history. Foreign family members aren’t listed.
Features relating to contacting the IC under test, e.g. probe heads; chucks: interfaces, e.g. between probe and tester
Testing of individual semiconductor devices: apparatus or methods therefor
Cutting or separating of wafers, substrates or parts of devices
Apparatus for monitoring, sorting, marking, testing or measuring: process monitoring, e.g. flow or thickness monitoring
About 3 years 1 month of term left · ends 12 Nov 2029 (estimated)
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