Methods for fabricating MOS devices having highly stressed channels
AssigneeAdvanced Micro Devices, Inc.
InventorsFrank Bin Yang, Rohit Pal, Michael J. Hargrove
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Abstract
Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.
Claims20
A method of fabricating an MOS transistor on and within a silicon-comprising substrate having a first surface, the method comprising:
- depositing a polysilicon layer overlying the first surface of the silicon-comprising substrate;
- amorphizing the polysilicon layer;
- forming a gate stack comprising a gate electrode fabricated from the polysilicon layer and having sidewalls, the gate stack disposed overlying the first surface of the silicon-comprising substrate;
- forming offset spacers adjacent the sidewalls of the gate electrode;
- etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate, the recesses exposing second surfaces of the silicon-comprising substrate;
- depositing a stress-inducing silicon nitride layer overlying the gate stack, the offset spacers, and the second surfaces;
- annealing the silicon-comprising substrate;
- removing the stress-inducing silicon nitride layer;
- and
- after removing the stress-inducing silicon nitride layer, epitaxially forming impurity-doped, silicon-comprising regions in the recesses.
A method for forming a semiconductor device comprising a silicon-comprising substrate, wherein the method comprises:
- depositing a polysilicon layer overlying the silicon-comprising substrate;
- amorphizing the polysilicon layer;
- etching the amorphized polysilicon layer to form a gate electrode;
- etching recesses into the substrate using the gate electrode as an etch mask;
- depositing a stress-inducing layer overlying the gate electrode after etching recesses into the substrate;
- annealing the silicon-comprising substrate;
- removing the stress-inducing layer;
- and
- after removing the stress-inducing layer, epitaxially growing impurity-doped, silicon-comprising regions in the recesses.
A method of fabricating an MOS transistor on and within a silicon-comprising substrate having a first surface, the method comprising:
- depositing a polysilicon layer overlying the first surface of the silicon-comprising substrate;
- amorphizing the polysilicon layer;
- forming a gate stack comprising a gate electrode fabricated from the polysilicon layer and having sidewalls, the gate stack disposed overlying the first surface of the silicon-comprising substrate;
- forming offset spacers adjacent the sidewalls of the gate electrode;
- etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate;
- depositing a stress-inducing silicon nitride layer overlying the gate stack, the offset spacers, and the recesses;
- annealing the silicon-comprising substrate;
- removing the stress-inducing silicon nitride layer;
- and
- after removing the stress-inducing silicon nitride layer, epitaxially forming impurity-doped, silicon-comprising regions in the recesses.
Dependencies are inferred from the claim text.