US 8,076,204 B2Granted

Graphene-based transistor

AssigneeInternational Business Machines Corporation

InventorsBrent A. Anderson, Edward J. Nowak

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Abstract

A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.

Claims20

Dependent claims

A method of manufacturing a field effect transistor comprising:

providing a silicon carbide substrate;
forming at least one pair of sidewalls conducive to graphitization on said silicon carbide substrate;
performing a solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein at least one graphene layer is formed on said silicon carbide substrate, said at least one graphene layer contiguously extending, in order, through a first horizontal graphene layer, a first vertical graphene layer, a second horizontal graphene layer, a second vertical graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene layer, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layers are formed by graphitization of said at least one pair of sidewalls;
forming an ion implantation blocking structure over a portion of said at least one graphene layer;
forming doped source and drain regions within said silicon carbide substrate;
removing said ion implantation blocking structure;
forming a gate dielectric over said portion of said at least one graphene layer;
and
forming a gate electrode directly on said gate dielectric layer.

6 more elements

A method of manufacturing a field effect transistor comprising:

providing a silicon carbide substrate;
forming at least one pair of sidewalls not conducive to graphitization on said silicon carbide substrate;
performing solid state graphitization on exposed surfaces of said silicon carbide substrate including said at least one pair of sidewalls, wherein a contiguous carbon-containing layer is formed on said silicon carbide substrate, said contiguous carbon-containing layer contiguously extending, in order, through a first horizontal graphene layer, a first vertical carbon layer having a structural arrangement different from a graphene layer, a second horizontal graphene layer, a second vertical carbon layer having a structural arrangement different from a graphene layer, and a third horizontal graphene layer that is coplanar with said first horizontal graphene layer, wherein said second horizontal graphene layer is vertically offset from said first and third graphene layers, and said first and second vertical graphene layer are formed by graphitization of said at least one pair of sidewalls;
forming an ion implantation blocking structure over a portion of said at least one graphene layer;
forming doped source and drain regions within said silicon carbide substrate;
removing said ion implantation blocking structure;
forming a gate dielectric over said portion of said at least one graphene layer;
and
forming a gate electrode directly on said gate dielectric layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/765,483Filed 22 Apr 2010 · division
Priority: 16 Jul 2007
Published: US 2010/0200840 A112 Aug 2010
Granted: 13 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/472
High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]: having lower bandgap active layer formed on top of wider…
H10D 30/6748
Group IV materials, e.g. germanium or silicon carbide: having a multilayer structure or superlattice structure

Family

Application11/778,209Parent of this division · filed 16 Jul 2007
US 2010/0200840 A1Pre-grant publication · published 12 Aug 2010
US 7,732,859 B2Parent of this division
US 2009/0020764 A1Published application
US 8,076,204 B2This patent

From the US filing history. Foreign family members aren’t listed.