US 8,076,199 B2Granted

Method and device employing polysilicon scaling

AssigneeSpansion LLC

InventorsShenqing Fang, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong

Life of this patent

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Abstract

A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

Claims14

Dependent claims

A method of fabricating polysilicon lines of a memory, comprising:

forming a layered stack on a core section and a peripheral section of a substrate, wherein the layered stack includes a charge trapping component that is positioned on the core section and the peripheral section, and a core polysilicon layer that is positioned on the charge trapping component;
removing a portion of the layered stack that is located at the peripheral section, wherein removing the layered stack from the peripheral section includes removing the core polysilicon layer from the peripheral section;
forming a peripheral polysilicon layer on the peripheral section and the layered stack of the core section such that the peripheral polysilicon is thicker than the core polysilicon layer;
removing a portion of the peripheral polysilicon layer that is located on the layered stack of the core section;
and
patterning individual polysilicon lines in the layered stack of the core section.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/370,950Filed 13 Feb 2009
Published: US 2010/0207191 A119 Aug 2010
Granted: 13 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors
H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 64/037
Of data-storage electrodes: comprising charge-trapping insulators