Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die

A method of making a semiconductor device, comprising:

• providing a base substrate having first and second opposing surfaces;
• forming a plurality of cavities and base leads between the cavities in the first surface of the base substrate, wherein the cavities create multiple rows of the base leads including a first set of base leads and a second set of base leads, wherein the second set of base leads includes a concave capture pad;
• forming a plurality of openings in the base substrate between the first set of base leads and second set of base leads;
• mounting a first semiconductor die to the base substrate and on the openings in the base substrate;
• stacking a second semiconductor die over the first semiconductor die;
• depositing a first insulating layer over the first semiconductor die, second semiconductor die, and base substrate;
• removing a portion of the second surface of the base substrate to separate the base leads;
• and
• forming an interconnect structure over the first insulating layer and base leads, the interconnect structure being electrically connected to the base leads and second semiconductor die.

A method of making a semiconductor device, comprising:

• providing a base substrate having a plurality of base leads in multiple rows, the base leads including a first set of base leads and a second set of base leads, wherein the second set of base leads includes a concave capture pad;
• mounting a first semiconductor die to the base substrate between the first set of the base leads and on the second set of the base leads;
• stacking a second semiconductor die over the first semiconductor die;
• depositing an insulating layer over the first semiconductor die, second semiconductor die, and base substrate;
• removing a portion of the base substrate to separate the base leads;
• forming an interconnect structure over the insulating layer and base leads, the interconnect structure being electrically connected to the base leads and the second semiconductor die;
• stacking a plurality of the semiconductor devices;
• and
• electrically connecting the stacked semiconductor devices through the interconnect structure and base leads.