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US 8,072,796 B2Granted
Memory with five-transistor bit cells and associated control circuit
AssigneeMeta Systems
InventorsJean Barbier, Olivier LePape, Philippe Piquet
Life of this patent
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Abstract
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
Claims19
A memory circuit, comprising:
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of bit cells;
- and
- a controller coupled to the plurality of bit lines and to the plurality of select lines, wherein the controller includes a power supply control circuit adapted to control the power supply voltage applied to the plurality of bit cells, wherein the controller is adapted to read a selected bit cell of the plurality of bit cells by a setting of a select line associated with the selected bit cell to a first level, and to set the selected bit cell by an activation of the select line associated with the selected bit cell to a second level, wherein the first level is lower than the second level,
- and
- wherein the power supply control circuit includes:
- a P transistor comprising a source and a drain, wherein the source of the P transistor is coupled to a power supply and wherein the drain of the P transistor is coupled to the plurality of bit cells;
- a first N transistor serially coupled to the P transistor, wherein the first N transistor is adapted to operate as a diode;
- and
- a second N transistor serially coupled to the first N transistor, wherein a source of the second N transistor is coupled to ground and wherein both the P transistor and second N transistor are driven by a reset signal.
8 more elements
An integrated circuit comprising:
- a memory block, the memory block having;
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of bit cells;
- a controller coupled to the plurality of bit lines and to the plurality of select lines, wherein the controller of the memory block further comprises a power supply control circuit adapted to control the power supply voltage-applied to the plurality of bit cells, and wherein the power supply control circuit includes:
- a P transistor having-a source coupled to a power supply and a drain coupled to the plurality of bit cells;
- a first N transistor serially coupled to the P transistor, wherein the first N transistor is adapted to operate as a diode;
- and
- a second N transistor serially coupled to the first N transistor, wherein a source of the second N transistor is coupled to ground and wherein both the P transistor and second N transistor are driven by a reset signal;
- a third N transistor coupled to the plurality of bit cells, and wherein a source of the third N transistor is coupled to ground;
- and
- a plurality of circuit elements correspondingly coupled to the plurality of bits cells.
9 more elements
A memory circuit, comprising:
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of bit cells;
- and
- a controller coupled to the plurality of bit lines and to the plurality of select lines, wherein the controller is adapted to perform a clear operation on the plurality of bit cells, wherein the clear operation includes a reduction of a power supply voltage applied to the plurality of bit cells to a level above zero volts and below a threshold voltage of access transistors of the plurality of memory cells, and wherein the controller is further adapted to selectively set the bit cells by selective activation of the plurality of select lines and by selective driving of the plurality of bit lines to logic zero.
2 more elements
Dependencies are inferred from the claim text.