Silicon based nanoscale crossbar memory
AssigneeThe Regents of the University of Michigan
InventorsWei Lu, Sung Hyun Jo, Kuk-Hwan Kim
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Abstract
The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
Claims51
A crossbar memory array, comprising:
- a first array of nanowires of a first material;
- a second array of nanowires of a different second material oriented at an angle with the first array;
- and
- a plurality of non-crystalline silicon nanostructures, each intersection of the first array and the second array including one of the non-crystalline silicon nanostructures disposed between a nanowire of the first material and a nanowire of the second material to form a resistive memory cell;
- wherein at least one of the plurality of non-crystalline silicon nanostructures is a nanoscale pillar providing a contact point between the first and second arrays at exactly one intersection.
A non-volatile solid state resistive device, comprising:
- a substrate;
- an n-type silicon second electrode on the substrate;
- a first electrode on the substrate at least partially vertically overlapping the second electrode;
- a p-type silicon body vertically stacked between the first electrode and the n-type silicon second electrode and in contact with the n-type silicon second electrode to form a PN diode;
- and
- a non-crystalline silicon nanostructure vertically stacked between the first electrode and the p-type silicon body.
A crossbar memory array, comprising:
- a first array of nanowires of a first material;
- a second array of nanowires of a different second material oriented at an angle with the first array;
- and
- a plurality of non-crystalline silicon nanostructures, each intersection of the first array and the second array including one of the non-crystalline silicon nanostructures disposed between a nanowire of the first material and a nanowire of the second material to form a resistive memory cell;
- wherein at least one of the plurality of non-crystalline silicon nanostructures is a nanowire providing contact points between the first and second arrays at a plurality of intersections.
A method for fabricating an array of resistive memory devices, comprising:
- forming a first array of parallel nanowires of a first material on a substrate;
- forming a plurality of non-crystalline silicon nanostructures on the first array of parallel nanowires;
- and
- forming a second array of parallel nanowires of a different second material on the plurality of non-crystalline silicon nanostructures and oriented at an angle with the first parallel array so that each intersection of the first array and the second array includes one of the non-crystalline silicon nanostructures disposed between a nanowire of the first material and a nanowire of the second material to form a resistive memory cell;
- wherein at least one of the plurality of non-crystalline silicon nanostructures comprises a nanoscale pillar providing a contact point between the first array and the second arrays at exactly one intersection.
A method for fabricating an array of resistive memory devices, comprising:
- depositing, on a substrate, a first layer of a first material;
- depositing, on the first layer, a second layer of a non-crystalline silicon;
- removing portions of the first layer and the second layer to form a first array of nanowires, each nanowire comprising a non-crystalline silicon nanowire on a nanowire of the first material;
- depositing a third layer of insulator material on the first array of nanowires;
- partially removing the third layer to expose the non-crystalline silicon nanowires;
- depositing a fourth layer of second material such that the non-crystalline silicon nanowires are in contact with the fourth layer;
- partially removing the fourth layer to form a second array of nanowires of the second material, the second array oriented at an angle with the first array, each intersection of the first and second arrays forming a resistive memory device, nanowires of the first and second materials acting as electrodes of the resistive memory device devices.
Dependencies are inferred from the claim text.