Three phase and polarity encoded serial interface

A serial interface transmitter circuit, comprising:

• first, second, and third conductors each having first and second ends;
• a plurality of current sources;
• a plurality of switches that selectively couple the current sources to the first ends of said first, second, and third conductors;
• and
• a plurality of impedances that couple together the second ends of the first, second, and third conductors;
• wherein current in the circuit flows in a predetermined polarity between exactly two of the first, second, and third conductors at any time, whereby an unused conductor is un-driven, thereby generating a data transmission state of the transmitter circuit, whereby a first data encoding state is defined by driving the current in a first polarity to a first set of conductors from the first end and a second data encoding state is defined driving the current in a second polarity to second set of conductors by the first end, wherein the first data encoding state is different from the second encoding state;
• a collector for collecting one or more transitions from the first encoding state to the second encoding state;
• and
• a map for grouping data bits based on the collected transitions.

A non-transitory computer-executable storage medium comprising program instructions which are computer-executable to implement data encoding, the storage media comprising:

• (a) program instructions that cause a transmission of a first signal in a first polarity and a first phase between two of a first, second, and third conductors, leaving a remaining conductor un-driven;
• (b) program instructions that cause a transmission of a second signal in a second polarity and a second phase between two of said first, second, and third conductors, leaving the remaining conductor un-driven, wherein the first polarity is different from the second polarity or the first phase is different than the second phase or the first polarity and the first phase are different from the second polarity and the second phase;
• wherein (a) defines a first data encoding state;
• wherein (b) defines a second data encoding state, wherein the first data encoding state is different from the second encoding state;
• wherein an occurrence of (a) and (b) defines a state transition in a data encoding state diagram, said state transition representing a logic data encoding and allows up to 2.3219 bits of data comprising log2(5)=In(5)/In(2), encoded in a single state transition;
• (c) program instructions that cause a collection one or more state transitions between the encoding states;
• and
• (d) program instructions that cause a map to be created for a group of data bits based on the collected state transitions.