Microprogrammed processor having mutiple processor cores using time-shared access to a microprogram control store
AssigneesConemtech AB, Imsys AB
InventorStefan Blixt
Life of this patent
Estimating the term…
Abstract
There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically includes at least two processor cores (10), and a common internal microprogram control store (20) including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable elements (30) for providing time-shared access to the microprogram control store by the processor cores.
Claims12
A microprogrammed multi-core processor, the microprogrammed processor being microcode controlled and comprising:
- at least two processor cores, each of said processor cores having at least one internal execution unit and an associated microinstruction register;
- a common internal microprogram control store connected to said microinstruction registers of said at least two processor cores, said common internal microprogram control store including microcode instructions for controlling at least the internal standard operation of said at least two processor cores, said microcode instructions controlling operation of said internal execution units;
- means for providing time-shared access to said microprogram control store by said at least two processor cores,
- wherein the microcode instructions from said common control store are loaded directly into said microinstruction registers of said at least two processor cores, contents of each of said microinstruction register directly controlling the associated said execution unit, thereby sharing resources of said control store of the microprogrammed processor, and
- wherein said at least two processor cores are separate and configured to execute different microprogram tasks independently of each other according to respective execution threads, said execution unit of each of said at least two processor cores determining a next microprogram address.
A method of operating a microprogrammed multi-core processor that is microcode controlled and having at least two processor cores, each of said processor cores having at least one internal execution unit and an associated microinstruction register, said method comprising the steps of:
- providing a common microprogram control store connected to the microinstruction registers of the at least two processor cores, said common microprogram control store including microcode instructions for controlling at least the internal standard operation of said at least two processor cores, said microcode instructions controlling operation of said internal execution units;
- providing access to said common microprogram control store by said at least two processor cores on time-shared basis,
- wherein the microcode instructions from said common control store are loaded directly into said microinstruction registers of said processor cores, contents of each of said microinstruction register directly controlling the associated said execution unit, thereby sharing resources of said control store of the microprogrammed processor;
- and
- configuring the at least two processor cores, which are separate, to execute different microprogram tasks independently of each other according to respective execution threads, the execution unit of each of the at least two processor cores determining a next microprogram address.
Dependencies are inferred from the claim text.