Content addressable memory array programmed to perform logic operations
AssigneeInternational Business Machines Corporation
InventorsLeland Chang, Gary S. Ditlow, Brian L. Ji, Robert K. Montoye
Life of this patent
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Abstract
A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.
Claims17
A memory device for performing logical operations on two or more input variables, the memory device comprising:
- a match line;
- a first memory cell coupled to the match line and including a first and second memory element, each memory element being coupled to a particular different logical product of a first input variable and a second input variable;
- and
- a second memory cell coupled to the match line and including a third and fourth memory element, each memory element being coupled to a particular logical product of the first input variable and the second input variable;
- wherein the first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.
A method of performing logical operations between two or more input variables, the method comprising:
- providing a first two-bit cell, the first two-bit cell including a first portion and a second portion, wherein the first and second portions both include a memory cell that includes two memory elements;
- coupling the first two-bit cell to a match line;
- coupling a first logical product of a first input variable and a second input variable to a cell in the first portion and coupling a second logical product of the first input variable and the second input variable to a cell in the second portion, the first and second logical product being different from one another;
- programming the memory elements to one of two different values based on a particular logical operation to be performed;
- and
- monitoring a parameter of the match line to determine a result of the logical operation.
A memory system comprising:
- a content addressable memory including a first memory cell coupled to a match line and including a first and second memory element, each memory element being coupled to a different particular logical product of the a first input variable and a second input variable, and a second memory cell coupled to the match line and including a third and fourth memory element, each memory element being coupled to a particular logical product of the first input variable and the second input variable, wherein the first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed;
- a match checking device coupled to the content addressable memory that determines if a particular input applied to the content addressable memory provides a logical 1 or logical zero as an output;
- and
- a decoder coupled to the content addressable memory that receives an input address and decodes at least two of the bits from the address into four unique outputs.
Dependencies are inferred from the claim text.