Decoding device, encoding/decoding device and recording/reproducing device

An encoding/decoding device comprising:

• an encoder comprising:
• an ECC encoder for creating an error correcting code word by interleaving a data string into n (n≧2) blocks of a data string at every m (m≧2) bit, generating a parity of an error correcting code from the interleaved data string of each block, and adding the parity of the error correcting code of each block to the data string;
• and
• a parity encoder for creating a parity bit at every predetermined number of bits of error correcting code words, and adding the parity bit to error correcting code words;
• a decoder comprising:
• a soft output decoder for decoding the encoded data string that is received to a code bit string, and outputting the code bit string and the likelihood of each bit;
• and
• an ECC decoding circuit for repeating an error correction decoding using an error correcting code of the code bit string of the soft output decoder and a correction decoding of the code bit string based on the likelihood according to the error detection using the parity bit,
• wherein the ECC decoding circuit comprises:
• an ECC decoder for performing error correction using the error correcting code of the code bit string of the soft output decoder;
• and
• a parity/likelihood correction unit for performing an error detection using the parity bit according to the failure of the decoding of the ECC decoder, and correcting the code bit string that is input to the ECC decoder depending on the likelihood according to the error detection result.

A recording/reproducing device comprises:

• a head for writing and reading data to/from a storage medium;
• an ECC encoder for interleaving a data string into n (n≧2) blocks of a data string, which is to be written to the storage medium, at every m (m≧2) bit, generating a parity of an error correcting code from the interleaved data string of each block, and adding the parity of the error correcting code of each block to the data string;
• a parity encoder for creating a parity bit at every predetermined number of bits of error correcting code words, adding the parity bit to error correcting code words and outputting the result to the head;
• a soft output decoder for decoding an encoded data string read from the head to a code bit string, and outputting the code bit string and the likelihood of each bit;
• and
• an ECC decoding circuit for repeating an error correction decoding using the parity of the error correcting code of the code bit string of the soft output decoder, and a correction decoding of the code bit string based on the likelihood according to the error detection using the parity bit,
• wherein the ECC decoding circuit comprises:
• an ECC decoder for performing error correction using the error correcting code of the code bit string of the soft output decoder;
• and
• a parity/likelihood correction unit for performing an error detection using the parity bit according to a failure of the decoding of the ECC decoder, and correcting the code bit string that is input to the ECC decoder depending on the likelihood according to the error detection result.