Multiple access for parallel turbo decoder
AssigneeNokia Corporation
InventorEsko Nieminen
Life of this patent
Estimating the term…
Abstract
A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding.
Claims48
A method comprising:
- providing a memory bank comprised of a plurality of memories, a first Butterfly network configured to apply memory addresses to the memory bank, and a second Butterfly network configured to pass data to or from the memory bank;
- and
- generating control signals for the first and second Butterfly networks in accordance with a multiple access rule to enable 2m-tuple parallel access to the memory bank, without memory access conflict, for a linear order and for an interleaved order, where m is an integer at least one.
A program of machine-readable instructions, embodied on a tangible memory and executable by a digital data processor, to perform actions directed toward controlling memory access, the actions comprising:
- generating a control signal for a first Butterfly network and for a second Butterfly network in accordance with a multiple access rule to enable 2m-tuple parallel access to a memory bank, without memory access conflict, for a linear order and for an interleaved order, where m is an interger at least one;
- and
- sending the control signals to the first and second Butterfly networks for respective linear order and interleaved order accesses;
- wherein the memory bank comprises a plurality of memories, the first Butterfly network is configured to apply memory addresses to the memory bank, and the second Butterfly network is configured to pass data to and from the memory bank.
An apparatus comprising:
- a memory bank comprising a plurality of memories;
- a first Butterfly network coupled to the memory bank and configured to apply memory addresses to the memory bank;
- a second Butterfly network coupled to the memory bank and configured to pass data to or from the memory bank;
- and
- a processor having a control output coupled to the first and the second Butterfly networks, configured to generate control signals for the first and second Butterfly networks in accordance with a multiple access rule to enable 2m-tuple parallel access to the memory bank, without memory access conflict, for a linear order and for an interleaved order, where m is an interger at least one.
Dependencies are inferred from the claim text.