Configuring routing in mesh networks

A system comprising:

• a processor comprising
• a plurality of processor tiles, each tile having a coordinate, each tile comprising
• a processor core, and
• a routing arbiter to determine a path for routing data through a multi-dimensional interconnection network that interconnects the processor cores and enables transfer of data among the processor cores;
• a memory controller having input/output ports that are coupled to corresponding input/output ports associated with some of the processor cores;
• and
• a first dimension register that is programmed to store information indicating the ordering of dimensions for routing data;
• wherein when each of the routing arbiters receives a packet, the routing arbiter queries the first dimension register to determine a dimension ordering policy, and determines an ordering of dimensions for routing the packet based on coordinates of the routing arbiter, destination coordinates of the packet, and the dimension ordering policy.

A processor, comprising:

• a plurality of processor tiles, each tile comprising a processor core;
• and
• an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions with a first ordering of dimensions used for routing data from an input/output device to the processor cores, and a second ordering of dimensions used for routing data from the processor cores to the input/output device, the second ordering of dimensions being different from the first ordering of dimensions;
• the plurality of processor cores comprising a two-dimensional array of processor cores arranged in rows and columns of processor cores, a first row of processor cores connected to input/output ports that are coupled to corresponding input/output ports of a peripheral device, wherein there are more data being sent from the peripheral device to the processor cores, and the first ordering of dimensions specifies that data are to be routed along a column direction followed by routing the data along a row direction.

A processor, comprising:

• a plurality of processor tiles, each tile comprising a processor core;
• and
• an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions with a first ordering of dimensions used for routing data from an input/output device to the processor cores, and a second ordering of dimensions used for routing data from the processor cores to the input/output device, the second ordering of dimensions being different from the first ordering of dimensions;
• the plurality of processor cores comprising a two-dimensional array of processor cores arranged in rows and columns of processor cores, a first row of processor cores connected to input/output ports that are coupled to a peripheral device, wherein there are more data being sent from the processor cores to the peripheral device, and the second ordering of dimensions specifies that data are to be routed along a row direction followed by routing the data along a column direction.