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US 8,046,729 B1Granted
Method and apparatus for composing and decomposing low-skew networks
AssigneeAltera Corporation
InventorsRyan Fung, David Galloway
Life of this patent
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Abstract
A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the second signal source can reach at least one element outside of the subset.
Claims16
A field programmable gate array (FPGA), comprising:
- an area associated with the FPGA comprising a plurality of locations within the area;
- and
- a dedicated composable/decomposable low-skew network operable to equalize delays from a source to the plurality of locations, the dedicated composable/decomposable low-skew network programmable to route one of 1) a single signal to the plurality of locations, and 2) a plurality of signals to the plurality of locations, wherein each of the plurality of signals is routed to a different one of the plurality of locations, and wherein a routing path of the composable/decomposable low-skew network is structured as an H-tree.
A field programmable gate array (FPGA), comprising:
- an area associated with the FPGA comprising a plurality of locations within the area;
- a dedicated composable/decomposable low-skew network operable to equalize delays to reduce skew between a source to the plurality of locations, the dedicated composable/decomposable low-skew network programmable to route one of 1) a single signal from an input pin to the plurality of locations and 2) a plurality of signals from a plurality of input pins to the plurality of locations, wherein each of the plurality of signals is routed to a different one of the plurality of locations, and wherein a routing path of the composable/decomposable low-skew network is structured as an H-tree.
Dependencies are inferred from the claim text.