Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof
AssigneeRealtek Semiconductor Corp.
InventorChien-Cheng Liu
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AssigneeRealtek Semiconductor Corp.
InventorChien-Cheng Liu
Estimating the term…
A first library cell and a second library cell each includes a plurality of metal layers, and a metal track direction of the odd metal layers of the first library cell is perpendicular to that of the odd metal layers of the second library cell. An integrated circuit design method applied to these library cells includes the steps of rotating the second library cell to cause the metal track direction of the odd metal layers of the second library cell to be parallel to that of the odd metal layers of the first library cell, and placing the first library cell and the second library cell in an identical integrated circuit design.
An integrated circuit design method applied to a plurality of library cells having a first library cell and a second library cell, where both the first library cell and the second library cell respectively have a plurality of metal layers, and a metal track direction of odd metal layers of the first library cell is perpendicular to that of odd metal layers of the second library cell, the integrated circuit design method comprising:
An integrated circuit design system applied to a plurality of library cells having a first library cell and a second library cell, the first library cell and the second library cell respectively having a plurality of metal layers, and a metal track direction of odd metal layers of the first library cell being perpendicular to that of odd metal layers of the second library cell, the integrated circuit design system comprising:
Dependencies are inferred from the claim text.
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Circuit design at the physical level: routing
Computing and data processing
About 3 years 4 months of term left · ends 12 Feb 2030 (estimated)
1. Field of the Invention
The present invention relates to an integrated circuit design method and a related system, and more particularly, to an integrated circuit design method for improving placement and routing (P&R) by rotating a metal track direction of metal layers of ultra high speed cells.
2. Description of the Prior Art
FIG. 1 (including 1A and 1B) is a diagram showing metal layers of a conventional normal cell and a conventional ultra high speed cell according to the prior art.
FIG. 2 (including 2A and 2B) is a diagram showing the power rails of the normal cell and the ultra high speed cell shown in FIG. 1.
FIG. 3 (including 3A, 3B, and 3C) is a diagram showing metal layers of a first library cell, a second library cell, and a rotated second library cell according to an embodiment of the present invention.
Please refer to FIG. 3. FIG. 3 (including 3A, 3B, and 3C) is a diagram showing metal layers of a first library cell, a second library cell, and a rotated second library cell according to an embodiment of the present invention. The first library cell consists of six metal layers M11-M16, as is shown in 3A. The second library cell includes six metal layers M21-M26, as is shown in 3B. A metal track direction of the odd metal layers M11, M13, and M15 of the first library cell is perpendicular to that of the odd metal layers M21, M23, and M25 of the second library cell. A metal track direction of the even metal layers M12, M14, and M16 of the first library cell is perpendicular to that of the even metal layers M22, M24, and M26 of the second library cell. In order to solve the problem of different metal track directions, the second library cell needs to be rotated to make the metal track direction of the odd metal layers M21′, M23′, and M25′ of the rotated second library cell be parallel to that of the odd metal layers M11, M13, and M15 of the first library cell. The metal track direction of the even metal layers M22′, M24′, and M26′ of the rotated second library cell is parallel to that of the even metal layers M12, M14, and M16 of the first library cell, as is shown in 3C.
Please refer to FIG. 4. FIG. 4 (including 4A, 4B, and 4C) is a diagram showing the power rails of the first library cell, the second library cell, and the rotated second library cell shown in FIG. 3. The power rail of the first library cell uses the first metal layer M11 as its power mesh, as is shown in 4A. The power rail of the second library cell uses the second metal layer M22 as its power mesh, as is shown in 4B. The power rail of the rotated second library cell uses the second metal layer M22′ as its power mesh, as is shown in 4C.
In the embodiment above, the first library cell can be a normal cell and the second library cell can be an ultra high speed cell, or the first library cell can be an ultra high speed cell and the second library cell can be a normal cell, but the configuration is not limited to this only and can be elements of other types. In addition, the abovementioned first library cell and the second library cell respectively consist of six metal layers. Those skilled in the art should understand that the number of the metal layers is not considered as a limitation of the present invention.