IP cores in reconfigurable three dimensional integrated circuits
OwnerNeal Solomoninventor
Life of this patent
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Abstract
The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) used to effect continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.
Claims11
A system for organizing IP cores in three dimensional FPGAs in a three dimensional system on a chip (3D SoC), comprising:
- a multi-layer FPGA;
- a multi-layer hybrid IC;
- SRAM memory components on at least one FPGA layer;
- LUTs in FPGA SRAM components;
- soft IP cores;
- wherein the IP cores include netlists;
- wherein at least one IP core accesses a memory component to change an FPGA layer program code;
- wherein an IP core program code is forwarded to a switch matrix apparatus on a FPGA layer;
- wherein the IP core program code activates at least one logic block array on a FPGA layer tile to reconfigure its interconnects from one ASIC position to another ASIC position when specific criteria are satisfied;
- and
- wherein when the FPGA layer in at least one logic block array are activated, they change their interconnection configuration to a new geometric position.
A system for organizing IP cores in three dimensional FPGAs in a three dimensional system on a chip, comprising:
- a multi-layer FPGA;
- a multi-layer hybrid IC;
- SRAM memory components on at least one FPGA layer;
- LUTs in FPGA SRAM components;
- soft IP cores including netlists;
- wherein at least one IP core accesses a memory component to change FPGA layer program code;
- wherein IP cores are constructed from IP core elements;
- wherein the IP core elements are modular components of program code for specific applications;
- wherein the IP core elements are combined into specific customized IP cores to solve specific multi-objective optimization problems (MOOPs);
- wherein an aggregation of IP core elements is organized to apply to at least one layer in a multi-layer FPGA or multi-layer hybrid IC to reconfigure at least one logic block array to a specific geometrical configuration;
- and
- wherein the IP core elements are reaggregated into different multiple combinations for specific applications.
A system for organizing IP cores in three dimensional FPGAs in a three dimensional system on a chip (3D SoC), comprising:
- a multi-layer FPGA;
- a multi-layer hybrid IC;
- SRAM memory components on at least one FPGA layer;
- LUTs in FPGA SRAM components;
- soft IP cores including netlists;
- wherein at least one IP core accesses a memory component to change an FPGA layer program code;
- wherein the an evolving environment changes a position, and presents a set of MOOPs to the 3D SoC;
- wherein the environment provides feedback to the multi-layer FPGA as they interact;
- wherein the 3D SoC models multiple scenarios and solution options and applies the solution options to evolutionary IP cores;
- wherein the evolutionary IP cores aggregate IP core elements;
- wherein the evolutionary IP cores are applied to the multi-layer FPGA;
- and
- wherein the multi-layer FPGA continuously transforms its geometrical configuration to adapt to the evolving environmental changes.
Dependencies are inferred from the claim text.