Waiver mechanism for physical verification of system designs
AssigneeLSI Corporation
InventorsViswanathan Lakshmanan, Michael Josephides, Lisa M. Miller
Life of this patent
Estimating the term…
Loading patent…
AssigneeLSI Corporation
InventorsViswanathan Lakshmanan, Michael Josephides, Lisa M. Miller
Estimating the term…
A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs and (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors.
A method of waiving verification failures, comprising the steps of:
A non-transitory storage medium for use in a computer to waive verification failures, the non-transitory storage medium recording a computer program that is readable and executable by the computer, the computer program comprising the steps of:
An apparatus comprising:
Dependencies are inferred from the claim text.