Memory device employing dual clocking for generating systematic code and method thereof

A memory device, comprising:

• at least a first bank divided between at least first and second memory cell array blocks, the first memory cell array block included in a first memory core block and the second memory cell array block included in a second memory core block;
• a first data patch unit configured to patch first parallel data read from the first memory core block in response to a first data patch pulse and output the first parallel data as first patch data;
• a first Cyclic Redundancy Check (CRC) generator configured to generate a plurality of first CRC values based on the first patch data and a plurality of second CRC values;
• a second data patch unit configured to patch second parallel data read from the second memory core block in response to a second data patch pulse and output the second parallel data as second patch data;
• a second CRC generator configured to generate the plurality of second CRC values based on the second patch data and the plurality of first CRC values;
• a first serializer configured to convert the first patch data to first serial data in response to the first data patch pulse, convert the plurality of first CRC values to a plurality of first CRC bits in response to a delayed second data patch pulse, and arrange the plurality of first CRC bits in a order for a number of bits of the first serial data to generate a first systematic code;
• and
• a second serializer configured to convert the second patch data to second serial data in response to the second data patch pulse, convert the plurality of second CRC values to a plurality of second CRC bits in response to a delayed first data patch pulse, and arrange the plurality of CRC bits in a order for a number of bits of the second serial data to generate a second systematic code.

A method, comprising:

• patching parallel data read from a memory core block in response to a first read pulse;
• generating a second read pulse delayed by a period of time from if the first read pulse is generated;
• generating the CRC code based on the parallel data in response to the second read pulse;
• and
• converting the parallel data to serial data in response to the first read pulse, and arranging the CRC code in a order for a number of bits of the serial data to generate a systematic code.

A method, comprising:

• patching first parallel data read from a first memory core block in response to a first data patch pulse and outputting the first parallel data as first patch data, the first memory core block including a first memory cell array block included in at least a first bank divided between the first memory cell array block and a second memory cell array block, the second memory cell array block included in a second memory core block;
• patching second parallel data read from the second memory core block in response to a second data patch pulse and outputting the second parallel data as second patch data;
• generating a plurality of first CRC values based on the first patch data and a plurality of second CRC values;
• generating the plurality of second CRC values based on the second patch data and the plurality of first CRC values;
• converting the first patch data to first serial data in response to the first data patch pulse, converting the plurality of first CRC values to a plurality of first CRC bits in response to a delayed second data patch pulse, arranging the plurality of first CRC bits in a order for a number of bits of the first serial data to generate a first systematic code;
• and
• converting the second patch data to second serial data in response to the second data patch pulse, converting the plurality of second CRC values to a plurality of second CRC bits in response to a delayed first data patch pulse, and arranging the plurality of second CRC bits in a order for a number of bits of the second serial data to generate a second systematic code.