Area efficient memory architecture with decoder self test and debug capability
AssigneeSTMicroelectronics Pvt. Ltd.
InventorPrashant Dubey
Life of this patent
Estimating the term…
Abstract
An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.
Claims19
An area efficient memory architecture with address decoder self test and debug capability, the architecture comprising:
- a memory core to store data;
- an input/output (I/O) block coupled to said memory core and structured to read data from and write data into said memory core;
- a memory control circuit coupled to said memory core and said I/O block to generate internal clock and control signals for proper memory operation;
- a decoder structured to receive address and control signals from said memory control circuit and generate an address output for read/write operation on said memory core;
- a test control circuit to generate a test control sequence for the decoder, to verify results of said test control sequence, and to generate a test status output;
- a reference generator coupled to the test control circuit and having a plurality of latches structured from the same type as memory cells in the memory core and configured to form a ring counter type shift register that is structured to generate a known valid address output corresponding to the decoder address output for the test control sequence, the reference generator latches coupled in series via dual pass gates in which first pass gates are structured to respond to complementary clock signals and are coupled in an odd and even arrangement;
- wherein second pass gates are coupled to odd and even wordlines and are structured to receive a latch signal from the test control circuit and in response thereto latch an output on the odd and even wordlines;
- and
- a comparator structured to compare the outputs from the decoder and the reference generator to identify whether a fault in the decoder has occurred.
A testing device to test an address decoder of a memory device, the testing device comprising:
- a test controller structured to provide a test control sequence to the decoder, to verify results of said test control sequence, and to generate a test status output;
- a reference generator coupled to the test controller and structured to generate a known valid address output corresponding to an address output of the decoder for said test control sequence, the reference generator comprising latches structured from the same type as memory cells in the memory core and coupled in series via dual pass gates that are structured to respond to complementary clock signals and are coupled in an odd and even arrangement to form a ring type shift register;
- wherein first pass gates are structured to respond to the complementary clock signals and second pass gates are coupled to odd and even wordlines and are structured to receive a latch signal from the test control circuit and in response thereto latch an output on the odd and even wordlines;
- and
- a comparator coupled to the decoder and the reference generator and structured to compare address outputs from the decoder and the reference generator to identify whether a fault in the decoder has occurred.
Dependencies are inferred from the claim text.