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US 8,046,651 B2Granted
Compare circuit receiving scan register and inverted clock flip-flop data
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.
Claims4
A device comprising;
- A. a scan data input lead;
- B. a scan clock lead;
- C. a scan enable lead,
- D. a scan register having a scan input coupled to the scan data input lead, a clock input coupled to the scan clock lead, a control input coupled to the scan enable lead, and a scan output;
- E. an inverter having an input connected to the scan clock lead and an output;
- F. a flip flop having a data input coupled to the scan data input lead, a clock input coupled to the output of the inverter, and a data output;
- and
- G. a compare circuit having a first data input coupled to the scan output of the scan register and a second data input coupled to the data output of the flip flop.
5 more elements
Dependencies are inferred from the claim text.