TAP sampling at double rate

An integrated circuit comprising:

• at least one test output configured to output test data off chip and at least one test input configured to receive a test clock from off chip;
• a plurality of circuitry to be tested;
• and
• at least one test control circuitry between said at least one test output and said plurality of circuitry to be tested,
• wherein said at least one test control circuitry is arranged to receive test data from said plurality of circuitry to be tested and to clock out said test data on a data line to said at least one test output with respect to a rising clock edge of said test clock and with respect to a falling clock edge of said test clock,
• wherein test data clocked out on said rising clock edge is directed to said at least one test control circuitry from a first one of said plurality of circuitry to be tested onto said data line, and is not directed from a second one of said plurality of circuitry to be tested, and
• wherein test data clocked out on said falling clock edge is directed to said at least one test control circuitry from the second one of said plurality of circuitry to be tested onto said data line and is not directed from the first one of said plurality of circuitry to be tested.

An integrated circuit comprising:

• at least one test input configured to receive test data from off chip and a test clock from off chip;
• a plurality of circuitry to be tested;
• a plurality of test control circuitry between said at least one test input and said plurality of circuitry to be tested, wherein said integrated circuit is arranged so that test data on a data line coupled from said test input to said plurality of test control circuitry is clocked in with respect to a rising clock edge of said test clock and with respect to a falling clock edge of said test clock, wherein test data clocked in or out on the rising clock edge is directed from or to said plurality of test control circuitry to or from respectively a first one of said plurality of test control circuitry and test data clocked in or out on the falling clock edge is directed to or from respectively a second one of said plurality of test control circuitry;
• and
• separating circuitry having at least one first flip flop which is clocked by a clock signal and at least one second flip flop which is controlled by an inverse of the clock signal, the separating circuitry connected to separate test data clocked in on the rising edge of the clock signal and test data clocked in on the falling edge of said clock signal,
• wherein test data on said data line clocked in on said rising clock edge is directed from said plurality of test control circuitry to a first one of said plurality of circuitry to be tested and test data on said data line clocked in on said falling clock edge is directed from said plurality of test control circuitry to a second one of said plurality of circuitry to be tested.

An integrated circuit comprising:

• at least one test input means for receiving test data from off chip and a test clock from off chip;
• a plurality of circuitry to be tested;
• test control means between said at least one test input and said plurality of circuitry to be tested, for controlling the test, said test control means arranged to receive test data from said test input;
• clocking means for clocking data on a data line in with respect to a rising clock edge of said test clock and clocking means for clocking data on said data line in with respect to a falling clock edge of said test clock;
• and
• directing means for directing test data on said data line clocked in on said rising clock edge from said test control means to a first one of said plurality of circuitry to be tested and concurrently directing test data on said data line clocked in on said falling clock edge from said test control means to a second one of said plurality of circuitry to be tested.

An integrated circuit comprising:

• at least one test output means for outputting test data off chip and test input means for receiving a test clock from off chip;
• a plurality of circuitry to be tested;
• test control means between said at least one test output and said plurality of circuitry to be tested, for controlling the test, said test control means arranged to receive test data from said plurality of circuitry to be tested;
• clocking means for clocking data out onto a data line with respect to a rising clock edge of said test clock and clocking means for clocking data out onto said data line with respect to a falling clock edge of said test clock;
• and
• directing means for directing test data clocked out on said rising clock edge to said test control means from a first one of said plurality of circuitry to be tested onto said data line and test data clocked out on said falling clock edge to said test control means to a second one of said plurality of circuitry to be tested onto said data line.