Transport subsystem for an MBIST chain architecture

An apparatus comprising:

• means for controlling a memory test, said memory test controlling means configured to (i) present one or more commands and (ii) receive one or more responses;
• means for transporting commands and responses to a plurality of memories, said transporting means configured to (i) receive said one or more commands, (ii) present said one or more responses, and (iii) generate one or more control signals, wherein said transporting means comprises transport circuits connected to form a pipeline chain with said memory test controlling means connected to an end of the chain and each of said transport circuits responds to a relevant one of said one or more commands, passes non-relevant ones of said one or more commands to another transport circuit, and passes said one or more responses along the chain to said memory test controlling means;
• and
• means for controlling said plurality of memories, said memory controlling means coupled to said transporting means and configured to (i) generate one or more memory access signals in response to said one or more control signals, (ii) receive one or more memory output signals from said plurality of memories in response to said one or more memory access signals, and (iii) generate said responses in response to said one or more memory output signals;
• wherein (i) each of said plurality of memories is independently sized and (ii) said memory test controlling means provides a common testing routine for said plurality of memories that is adjusted for the size of each of said plurality of memories by said memory controlling means.

A method of transporting information in a memory built-in self test (MBIST) chain architecture comprising:

• generating a reset command, one or more initialization commands, and a sequence of test commands;
• resetting one or more transport circuits in response to said reset command, wherein said transport circuits are connected to form a pipeline chain with a controller connected to an end of the chain, said commands are passed along the chain from said controller, and one or more responses are passed along the chain to said controller;
• initializing said one or more transport circuits in response to said one or more initialization commands;
• and
• generating said one or more response in response to testing one or more memories coupled to said one or more transport circuits based upon said sequence of test commands.