Cycle accurate fault log modeling for a digital system

A fault log modeling system for modeling a real-time fault log of a digital system, comprising:

• a fault injector module implemented on a computer processor, said fault injector module operative to inject at least first, second, and third faults into one or both of a data path and a control path of said digital system;
• and
• a fault log modeler logically associated with said fault injector module, wherein said fault log modeler operates to:
• spawn first, second, and third tracking threads for said first, second, and third faults, respectively;
• detect that said first fault is not used by said digital system and, in response, terminate said first tracking thread;
• synchronize said second and third tracking threads;
• and
• input said second and third tracking threads into a fault logging specification to model a behavior for each of said second and third faults to calculate a fault log model.

A computer program product comprising a non-transitory computer useable medium and computer readable code embodied on the computer useable medium for performing accurate modeling of a real-time fault log of a computer processor, the computer readable code comprising:

• non-transitory computer readable program code devices configured to cause a computer to inject one or more faults into at least one of a data path and a control path of said computer processor;
• non-transitory computer readable program code devices configured to cause the computer to track each said fault injected into said data path or said control path;
• non-transitory computer readable program code devices configured to cause the computer to synchronize said faults at a predefined synchronization point, wherein said predefined synchronization point comprises a predetermined clock cycle selected as a function of one or more logging delays between when said faults are injected into said data path and when said faults reach a logging point for logging in said real-time fault log of said computer processor;
• non-transitory computer readable program code devices configured to cause the computer to generate a fault log model of said faults according to a fault logging specification;
• and
• non-transitory computer readable program code devices configured to cause the computer to compare said fault log model against said real-time fault log of said computer processor to validate one or more elements of fault detection and logging logic for said real-time fault log.