Microcomputer system with reduced power consumption

A microcomputer system comprising:

• a main CPU section including a main CPU that operates upon receiving a main clock signal;
• a main nonvolatile memory element that is mounted on the main CPU section;
• a main volatile memory element that is mounted on the main CPU section, and in which control information is stored by the main CPU;
• a sub-CPU section including a sub-CPU, the sub-CPU section having a smaller number of circuit gates than the main CPU section;
• a sub-oscillator circuit that oscillates and outputs a sub-clock signal, which has a frequency lower than that of the main clock signal and is supplied to the sub-CPU section, the sub-oscillator circuit being configured to change over between a continuous mode for continuous oscillation and an intermittent mode for intermittent oscillation;
• and
• a power supply control circuit that is mounted in the sub-CPU section, and controls a power supply to at least a part of the main CPU section,
• wherein the main CPU is configured to, when the main CPU determines that an operation stop condition of the main CPU is satisfied, write and store the control information that is stored in the main volatile memory element in the main nonvolatile memory element, and give an operation stop notification to the sub-CPU,
• wherein the sub-CPU is configured to stop the power supply to at least a part of the main CPU section and set the sub-oscillator circuit to an intermittent mode, when the sub-CPU recognizes the operation stop notification,
• wherein the sub-CPU is configured to check whether an operation start condition of the main CPU section is satisfied in a period where the sub-clock signal is supplied,
• wherein, the sub-CPU is configured to change over the sub-oscillator circuit to the continuous mode and restart the power supply to at least a part of the main CPU section, when the operation start condition is satisfied, and
• wherein the main CPU is configured to rewrite the control information that is stored in the main nonvolatile memory element in the main volatile memory element, and execute processing based on the control information, when the main CPU starts upon restarting of the power supply.

A microcomputer system comprising:

• a main CPU section including a main CPU that operates upon receiving a main clock signal;
• a sub-CPU section including a sub-CPU, the sub-CPU section having a smaller number of circuit gates than the main CPU section;
• a sub-oscillator circuit that oscillates and outputs a sub-clock signal, which has a frequency lower than that of the main clock signal and is supplied to the sub-CPU section, the sub-oscillator circuit being configured to change over between a continuous mode for continuous oscillation and an intermittent mode for intermittent oscillation;
• a main volatile memory element in which control information is stored by the main CPU, and which is accessible by both of the main CPU and the sub-CPU;
• a main nonvolatile memory element that is accessible by both of the main CPU and the sub-CPU;
• a sub-volatile memory element in which I/O control information is stored by the sub-CPU, and which has a storage capacity smaller than that of the main volatile memory element;
• and
• a power supply control circuit that is mounted in the sub-CPU section, controls a power supply to at least a part of the main CPU section, and controls a power supply to the main volatile memory element and the main nonvolatile memory element,
• wherein the main CPU is configured to give an operation stop notification to the sub-CPU, when the main CPU determines that an operation stop condition of the main CPU is satisfied,
• wherein the sub-CPU is configured to, when the sub CPU recognizes the operation stop notification, stop the power supply to at least a part of the main CPU section, write and store the control information that is stored in the main volatile memory element in the main nonvolatile memory element, write and store the I/O control information, which is used while the power supply to at least a part of the main CPU section stops, in the sub-volatile memory element, and thereafter stop the power supply to the main volatile memory element and the main nonvolatile memory element, set the sub-oscillator circuit to an intermittent mode, and check whether an operation start condition of the main CPU section is satisfied in a period during which the sub-clock signal is supplied,
• wherein the sub-CPU is configured to, when the operation start condition is satisfied, change over the sub-oscillator circuit to the continuous mode, restart the power supply to the main volatile memory element and the main nonvolatile memory element, rewrite the control information that is stored in the main nonvolatile memory element in the main volatile memory element, rewrite the I/O control information that is used while the power supply to the main CPU section is stopped in the main volatile memory element, and thereafter restart the power supply to the main CPU section, and
• wherein the main CPU is configured to execute a process based on the rewritten control information, when the main CPU starts upon restating the power supply.

A microcomputer system comprising:

• a main CPU section including a main CPU that operates upon receiving a main clock signal;
• a sub-CPU section including a sub-CPU, the sub-CPU section having a smaller number of circuit gates than the main CPU section;
• a sub-oscillator circuit that oscillates and outputs a sub-clock signal, which has a frequency lower than that of the main clock signal and is supplied to the sub-CPU section;
• a main volatile memory element in which control information is stored by the main CPU, and which is accessible by both of the main CPU and the sub-CPU;
• a main nonvolatile memory element that is accessible by both of the main CPU and the sub-CPU;
• a sub-volatile memory element in which I/O control information is stored by the sub-CPU, and which has a storage capacity smaller than that of the main volatile memory element;
• and
• a power supply control circuit that is mounted in the sub-CPU section , controls a power supply to at least a part of the main CPU section, and controls a power supply to the main volatile memory element and the main nonvolatile memory element,
• wherein the main CPU gives an operation stop notification to the sub-CPU, when the main CPU determines that an operation stop condition of the main CPU is satisfied, and
• wherein the sub-CPU is configured to, when the sub-CPU recognizes the operation stop notification, stop the power supply to at least a part of the main CPU section, write and store the control information that is stored in the main volatile memory element in the main nonvolatile memory element, write and store the I/O control information, which is used while the power supply to at least a part of the main CPU section stops, in the sub-volatile memory element, and thereafter stop the power supply to the main volatile memory element and the main nonvolatile memory element.

A microcomputer system comprising:

• a main CPU section including a main CPU that operates upon receiving a main clock signal;
• a sub-CPU section including a sub-CPU, the sub-CPU section having a smaller number of circuit gates than the main CPU section;
• a sub-oscillator circuit that oscillates and outputs a sub-clock signal, which has a frequency lower than that of the main clock signal and is supplied to the sub-CPU section;
• a main volatile memory element in which control information is stored by the main CPU, and which is accessible by both of the main CPU and the sub-CPU;
• a main nonvolatile memory element that is accessible by both of the main CPU and the sub-CPU;
• a sub-volatile memory element in which I/O control information is stored by the sub-CPU, and which has a storage capacity smaller than that of the main volatile memory element, and
• a power supply control circuit that is mounted in the sub-CPU section , controls a power supply to at least a part of the main CPU section, and controls a power supply to the main volatile memory element and the main nonvolatile memory element,
• wherein the sub-CPU is configured to check whether an operation start condition of the main CPU section is satisfied while the power supply to at least a part of the main CPU section and a power supply to the main volatile memory element and the main nonvolatile memory element are stopped,
• wherein the sub-CPU is configured to, when the operation start condition is satisfied, restart the power supply to the main volatile memory element and the main nonvolatile memory element, rewrite the control information, which had been previously written and stored in the main nonvolatile memory element, in the main volatile memory element, rewrite the I/O control information, which is used while the power supply to at least the main part of the CPU section stops and is stored in the sub-volatile memory element, in the main volatile memory element, and thereafter restart the power supply to at least the main part of the CPU section, and
• wherein the main CPU is configured to execute a process based on the rewritten control information stored in the main volatile element when the power supply to the main CPU is restarted.