Reset-tolerant authentication device

An authentication device comprising:

• a processor having a reset input;
• a trigger source coupled to the reset input;
• and
• interface circuitry for outputting codes generated by the processor;
• wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;
• and
• wherein the processor comprises an internal random access memory and the processor is configured such that a given reset applied to the reset input does not affect contents of the internal random access memory.

An authentication device comprising:

• a processor having a reset input;
• a trigger source coupled to the reset input;
• and
• interface circuitry for outputting codes generated by the processor;
• wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;
• the device further comprising power-up circuitry coupled to the trigger source;
• wherein the power-up circuitry comprises a first resistor coupled between the reset input and a supply voltage and a second resistor coupled between the reset input and a ground potential.

A method for use in an authentication device comprising a processor and a trigger source coupled to a reset input of the processor, the method comprising the steps of:

• analyzing a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source;
• and
• outputting a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;
• wherein the analyzing step utilizes information stored in a register file of the processor to identify a particular one of a number of different possible causes for the given reset.

An authentication system comprising:

• a plurality of authentication devices;
• at least one host device configured for communication with one or more of the authentication devices;
• and
• an authentication server configured for communication with the host device;
• wherein at least one of the authentication devices comprises a processor and a trigger source coupled to a reset input of the processor, said authentication device being configured to analyze a given reset to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to output a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;
• wherein the code is provided to the host device and communicated by the host device to the authentication server for authentication;
• and
• wherein the processor analyzes the given reset by examining information stored in a register file of the processor to identify a particular one of a number of different possible causes for the given reset.

An authentication device comprising:

• a processor having a reset input;
• a trigger source coupled to the reset input;
• and
• interface circuitry for outputting codes generated by the processor;
• wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;
• and
• wherein the analysis of the given reset further includes determining if there is a legitimate cause of the given reset by examining sets of one or more bits of state information stored in one or more registers of a register file of the processor, and wherein each of the sets of one or more bits of state information being in a particular configuration is representative of a different possible legitimate cause for the given reset.

An authentication device comprising:

• a processor having a reset input;
• a trigger source coupled to the reset input;
• and
• interface circuitry for outputting codes generated by the processor;
• wherein the processor is configured to analyze a given reset applied to the reset input to determine if the reset is an inadvertent reset or a reset generated by the trigger source, and to generate a code responsive to the reset if the reset is determined to be a reset generated by the trigger source;
• and
• wherein the analysis of the given reset further comprises reading at least one of a signature and a checksum from a random access memory and comparing said at least one of a signature and a checksum to at least one of a corresponding respective hardcoded signature and a computed checksum.