System-on-a-chip (SoC) security using one-time programmable memories
AssigneeMarvell International Ltd.
InventorsWeishi Feng, Marcus Carlson, Pantas Sutardja, Bin Ni
Life of this patent
Estimating the term…
Abstract
Apparatus having corresponding methods and computer programs comprise: a processor; a test interface that is in communication with the processor only when the test interface is enabled; a first one-time-programmable (OTP) memory; and a non-volatile memory to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to test the first OTP memory; wherein the boot code causes the processor to enable the test interface when the first OTP memory has not been programmed; and wherein the boot code causes the processor to disable the test interface when the first OTP memory has been programmed.
Claims11
An apparatus comprising:
- a processor;
- a test interface in communication with the processor only when the test interface is enabled;
- a first one-time-programmable (OTP) memory, wherein the test interface is disabled when the first OTP memory has been programmed;
- a non-volatile memory configured to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to test the first OTP memory, and wherein the boot code causes the processor to enable the test interface when the first OTP memory has not been programmed;
- and
- a second OTP memory,
- wherein the boot code causes the processor to at least one of
- disable programmability of the second OTP memory when the first OTP memory has been programmed,
- enable programmability of the second OTP memory based on a password, or
- enable the test interface when the second OTP memory has been programmed.
An apparatus comprising:
- a processor;
- a test interface in communication with the processor only when the test interface is enabled;
- a first one-time-programmable (OTP) memory, wherein the test interface is disabled when the first OTP memory has been programmed;
- a non-volatile memory configured to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to test the first OTP memory, and wherein the boot code causes the processor to enable the test interface when the first OTP memory has not been programmed;
- and
- a second OTP memory, wherein the boot code causes the processor to disable programmability of the second OTP memory when the first OTP memory has been programmed,
- wherein the boot code causes the processor to enable programmability of the second OTP memory based on a password, and wherein the boot code causes the processor to enable the test interface when the second OTP memory has been programmed.
A method comprising:
- testing a first one-time-programmable (OTP) memory;
- enabling communication between a test interface and a processor when the first OTP memory has not been programmed;
- disabling communication between the test interface and the processor when the first OTP memory has been programmed;
- and
- at least one of
- disabling programmability of a second OTP memory when the first OTP memory has been programmed,
- enabling programmability of the second OTP memory based on a password, or
- enabling communication between the test interface and the processor when the second OTP memory has been programmed.
A method comprising:
- testing a first one-time-programmable (OTP) memory;
- enabling communication between a test interface and a processor when the first OTP memory has not been programmed;
- disabling communication between the test interface and the processor when the first OTP memory has been programmed;
- disabling programmability of a second OTP memory when the first OTP memory has been programmed;
- enabling programmability of the second OTP memory based on a password;
- and
- enabling communication between the test interface and the processor when the second OTP memory has been programmed.
Dependencies are inferred from the claim text.