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US 8,046,569 B2Granted
Processing element having dual control stores to minimize branch latency
AssigneeHewlett-Packard Development Company, L.P.
InventorMichael L. Ziegler
Life of this patent
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Abstract
Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce or avoid branch penalties (zero penalty branches).
Claims20
A system comprising:
- a first memory for storing a first plurality of words;
- a second memory for storing a second plurality of words;
- a register for storing a current word, wherein the current word comprises a first address of a next possible word from the first memory and a second address of a next possible word from the second memory;
- and
- a multiplexer that selects one of the next possible word from the first memory and the next possible word from the second memory to be a next current word during a time period;
- wherein the next possible word corresponding to the first address and the next possible word corresponding to the second address are provided to the multiplexer during the time period.
3 more elements
A method comprising:
- storing a first word in a computer readable register during a first time period, wherein the first word comprises a first address of a first next possible word from a first computer readable memory and a second address of a second next possible word from a second computer readable memory;
- retrieving the first next possible word from the first computer readable memory during a second time period based on the first address;
- retrieving the second next possible word from the second computer readable memory during the second time period based on the second address;
- and
- executing the first word to determine which of the first next possible word and the second next possible word will be subsequently stored in the computer readable register during the second time period.
2 more elements
A non-transitory computer readable storage medium on which is embedded a data structure operative to control a plurality of execution units to manage packets in a network, said data structure comprising a set of instructions to:
- store a first word in a computer readable register during a first time period, wherein the first word comprises a first address of a first next possible word from a first computer readable memory and a second address of a second next possible word from a second computer readable memory, wherein the second computer readable memory is separate from the first computer readable memory;
- retrieve the first next possible word from the first computer readable memory during a second time period based on the first address;
- retrieve the second next possible word from the second computer readable memory during the second time period based on the second address;
- and
- execute the first word to determine which of the first next possible word and the second next possible word will be subsequently stored in the computer readable resister during the second time period.
2 more elements
Dependencies are inferred from the claim text.