Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation
AssigneeCore Logic, Inc.
InventorsHoon Mo Yang, Man Hwee Jo, Il Hyun Park, Ki Young Choi
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Abstract
Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.
Claims13
A system for controlling a processor element (PE) structure comprising:
- a PE structure comprising two or more PEs in communication with each other to form a floating point unit (FPU)-processing element;
- a floating point-reconfigurable array (FP-RA) control circuit in communication with the PE structure to control the PE structure to perform FP arithmetic;
- and
- a configuration cache in communication with the FP-RA control circuit to store a context word used by the PE structure to perform the FP arithmetic operations,
- wherein when the FP arithmetic requires a multi-cycle operation, the configuration cache inputs an entry point to the FP-RA control circuit and the FP-RA control circuit generates the context word for each cycle of the multi-cycle operation.
The system of 1, wherein the FP-RA control circuit comprises a finite state machine (FSM) based control circuit.
Dependencies are inferred from the claim text.