Nonvolatile semiconductor memory device with advanced multi-page program operation

A programming method in a multilevel flash memory for which a memory cell array is divided into a plurality of banks, the method comprising:

• preparing a cache block associated with each of said plurality of banks;
• sequentially programming cache blocks, except a cache block allocated to a last bank of said plurality of banks, with MSB page data sequentially loaded through corresponding page buffers, programming said MSB page data after an LSB page program is performed directly into a selected block without passing through a cache block;
• copying said MSB page data programmed in said cache blocks back to the corresponding page buffers in response to a predetermined program command after the MSB page data is loaded into the last page buffer;
• and
• simultaneously programming corresponding blocks of said banks with said MSB page data contained into all of said page buffers.

A nonvolatile semiconductor memory device programming data including a least significant bit (LSB) page and a most significant bit (MSB) page, the device comprising:

• a memory cell array divided into N banks;
• N page buffers, each respectively associated with a corresponding one of the N banks and being configured to load a page of data;
• and
• N caches, each respectively associated with a corresponding one of the N banks and being configured to receive data programmed from a corresponding one of the N page buffers,
• wherein each one N page buffers is further configured to program an LSB page directly to the corresponding one of the N banks without passing through the corresponding one of the N caches, and
• each one of the 1st through N−1th page buffers is further configured to program an MSB page to the corresponding one of the N banks through the corresponding one of the N caches.

A method of programming multi-level data including N pages of most significant bit (MSB) data to a nonvolatile semiconductor memory device having a memory cell array divided into 1st through Nth banks, the method comprising:

• sequentially loading an ith page of MSB data to an ith page buffer, and then programming the ith page of MSB data from the ith page buffer to an ith cache uniquely associated with an ith bank, wherein “i” ranges from 1 to N−1, wherein the respective programming of the 1st through N−1th pages of MSB data from the 1st through N−1th page buffers to the 1st through N−1th caches is performed using single-level cell (SLC) programming;
• loading a Nth page of MSB data to an Nth page buffer;
• and then,
• simultaneously and respectively programming the 1st through Nth pages of MSB data from 1st through Nth page buffers to the 1st through Nth banks using multi-level cell (MLC) programming;
• and
• after sequentially and respectively loading the 1st through N−1th pages of MSB data to the 1st through N−1th page buffers, and programming the 1st through N−1th pages of MSB data from the 1st through N−1th page buffers to the 1st through N−1th caches, copying back the 1st through N−1th pages of MSB data from the 1st through N−1th caches to the 1st through N−1th page buffers before loading an Nth page of MSB data to an Nth page buffer.

A method programming multi-level cell (MLC) data to nonvolatile semiconductor memory having an array of MLC memory cells divided into N banks, wherein each one of the 1st through Nth banks is programmed through at least one of corresponding 1st through Nth page buffers and 1st through Nth caches, the method comprising:

• preparing a cache block for the 1st through N−1th banks by sequentially programming 1st through N−1th pages of MLC data from the 1st through N−1th page buffers to the 1st through N−1th caches;
• loading an Nth page of MLC data to the Nth page buffer;
• and then,
• simultaneously and respectively programming the 1st through Nth pages of MLC data from the 1st through Nth pages buffers to the 1st through Nth banks;
• and
• before simultaneously and respectively programming the 1st through Nth pages of MLC data from the 1st through Nth pages buffers to the 1st through Nth banks, copying back the cache block by respectively copying back the 1st through N−1th pages of MLC data from the 1st though N−1th caches to the 1st through N−1th page buffers.