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US 8,046,516 B2Granted
Cache coherent switch device
AssigneeIntel Corporation
InventorRamakrishna Saripalli
Life of this patent
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Abstract
In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a switch device to be coupled between a first peripheral and a processor, the switch device to be coupled to the first peripheral by a first interconnect of a first communication protocol that provides for cache coherent transactions and non-cache coherent transactions and to the processor by a second interconnect of the first communication protocol, the switch device to handle cache coherency of the first communication protocol for the first peripheral, wherein the first peripheral is to handle only non-cache coherent transactions.
A method comprising:
- receiving in a switch, from a first peripheral device coupled to the switch, a transaction directed to a processor coupled to the switch;
- determining in the switch if the transaction is a cache coherent transaction and if so, performing coherent-related transactions related to the cache coherent transaction including snooping cache transactions of the processor and invalidating a location in a cache of the processor corresponding to the cache coherent transaction if the cache coherent transaction is destined for the location, wherein the switch and the first peripheral device are native devices of a first communication protocol;
- and
- after handling responses to the coherent-related transactions in the switch, forwarding the transaction to the processor.
1 more element
A system comprising:
- a first processor node to perform operations on data and including a plurality of cores and a memory controller to couple with a first memory;
- a first peripheral device including non-coherent logic to handle non-coherent transactions and first logic to issue cache coherent transactions but not to handle the cache coherent transactions;
- a switch device coupled to the first peripheral device by a first point-to-point interconnect of a first communication protocol that provides for cache coherent transactions and non-cache coherent transactions and to the first processor node by a second point-to-point interconnect of the first communication protocol, the switch device to handle cache coherency of the first communication protocol for the first peripheral device;
- a second processor node to perform operations on data and including a plurality of cores and a memory controller to couple with a second memory;
- and
- a chipset coupled to the second processor node by a third point-to-point interconnect of the first communication protocol.
3 more elements
Dependencies are inferred from the claim text.