Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features

A memory controller comprising:

• a page crossing detect logic including an address incrementer configured to generate a next address in a current burst from a current address in the current burst, wherein said page crossing detect logic is configured to generate a signal indicating whether the current burst will cross a memory page boundary based on the current address and the next address;
• a lookahead logic configured to detect an early burst termination on the last transfer of the current burst, wherein said look ahead logic is configured to receive one or more transaction signals and one or more transfer type signals from each of a plurality of ports, latch the one or more transaction signals from each of the plurality of ports, multiplex the latched transaction signals in response to a control signal, and multiplex the one or more transfer type signals received from the plurality of ports in response to the control signal;
• and
• one or more slave ports configured to provide a first sideband signal configured to specify a burst length for a respective port and a second sideband signal configured to enable the first sideband signal in a first state and disable the first sideband signal in a second state, wherein the memory controller is configured to artificially terminate bursts crossing page boundaries and handle the artificially terminated bursts as bursts that terminated early.