US 8,046,400 B2Granted

Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor

AssigneeVIA Technologies, Inc.

InventorsTom Elmer, Terry Parks

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Abstract

A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution to a rounding determination and relative to the PC field. If none of the conditions exists, the FPU makes the rounding determination based on the smaller addend and the PC field, and selectively rounds the sum based on the rounding determination. If any conditions exist, the FPU saves the sum and rounding information derived from the addends, and signals the instruction dispatcher to re-dispatch the instruction. On re-dispatch, the FPU makes the rounding determination based on the saved rounding information and the PC field, and selectively rounds the sum based on the rounding determination.

Claims24

Dependent claims

A microprocessor, comprising:

an x87 Floating Point Control Word (FPCW) including a Precision Control (PC) field programmable for specifying a precision of floating point (FP) calculations made by a FP unit (FPU) of the microprocessor;
an instruction dispatcher, configured to dispatch an x87 FP addition instruction (FPADD) to the FPU, the FPADD having first and second FP addends, wherein mantissas of the first and second addends potentially include bits of lesser arithmetic significance than a precision specified by the PC field;
and
the FPU, configured to:
add the first and second addends to generate a sum;
determine whether at least one of a set of predetermined conditions exists in the first and second addends with respect to their contribution to a rounding determination of the sum and relative to the precision specified by the PC field;
if none of the set of predetermined conditions exists:
(1) make the rounding determination based on bits of the mantissa of the smaller of the first and second addends and the precision specified by the PC field;
and
(2) selectively round up the sum based on the rounding determination for generating a final result of the FPADD;
and
if at least one of the set of predetermined conditions exists:
(1) derive rounding information from the first and second addends, save the sum, and save the rounding information;
(2) signal the instruction dispatcher to re-dispatch the FPADD to the FPU;
and
(3) in response to the instruction dispatcher re-dispatching the FPADD to the FPU:
(a) make the rounding determination based on the saved rounding information and the precision specified by the PC field;
and
(b) selectively round up the sum based on the rounding determination for generating the final result.

16 more elements

A method for processing an x87 floating point (FP) addition instruction (FPADD) in a microprocessor having a FP unit (FPU), an instruction dispatcher, and an x87 Floating Point Control Word (FPCW) including a Precision Control (PC) field programmable for specifying a precision of FP calculations made by the FPU, the method comprising:

dispatching initially an x87 FP addition instruction (FPADD) to the FPU, the FPADD having first and second FP addends, wherein mantissas of the first and second addends potentially include bits of lesser arithmetic significance than a precision specified by the PC field;
adding the first and second addends to generate a sum;
determining whether at least one of a set of predetermined conditions exists in the first and second addends with respect to their contribution to a rounding determination of the sum and relative to the precision specified by the PC field;
if none of the set of predetermined conditions exists:
(1) making the rounding determination based on bits of the mantissa of the smaller of the first and second addends and the precision specified by the PC field;
and
(2) selectively rounding up the sum based on the rounding determination for generating a final result of the FPADD;
and
if at least one of the set of predetermined conditions exists:
(1) deriving rounding information from the first and second addends, saving the sum, and saving the rounding information;
(2) signaling the instruction dispatcher to re-dispatch the FPADD to the FPU;
and
(3) in response to the instruction dispatcher re-dispatching the FPADD to the FPU:
(a) making the rounding determination based on the saved rounding information and the precision specified by the PC field;
and
(b) selectively rounding up the sum based on the rounding determination for generating the final result.

13 more elements

A computer program product for use with a computing device, the computer program product comprising:

a computer readable storage medium, having computer readable program code embodied in said computer readable storage medium, for providing a microprocessor, said computer readable program code comprising:
first program code for providing an x87 Floating Point Control Word (FPCW) including a Precision Control (PC) field programmable for specifying a precision of floating point (FP) calculations made by a FP unit (FPU) of the microprocessor;
second program code for providing an instruction dispatcher, configured to dispatch an x87 FP addition instruction (FPADD) to the FPU, the FPADD having first and second FP addends, wherein mantissas of the first and second addends potentially include bits of lesser arithmetic significance than a precision specified by the PC field;
and
third program code for providing the FPU, configured to:
add the first and second addends to generate a sum;
determine whether at least one of a set of predetermined conditions exists in the first and second addends with respect to their contribution to a rounding determination of the sum and relative to the precision specified by the PC field;
if none of the set of predetermined conditions exists:
(1) make the rounding determination based on bits of the mantissa of the smaller of the first and second addends and the precision specified by the PC field;
and
(2) selectively round up the sum based on the rounding determination for generating a final result of the FPADD;
and
if at least one of the set of predetermined conditions exists:
(1) derive rounding information from the first and second addends, save the sum, and save the rounding information;
(2) signal the instruction dispatcher to re-dispatch the FPADD to the FPU;
and
(3) in response to the instruction dispatcher re-dispatching the FPADD to the FPU:
(a) make the rounding determination based on the saved rounding information and the precision specified by the PC field;
and
(b) selectively round up the sum based on the rounding determination for generating the final result.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/100,583Filed 10 Apr 2008
Published: US 2009/0259708 A115 Oct 2009
Granted: 25 Oct 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 7/49942
Denomination or exception handling, e.g. rounding or overflow: significance control
G06F 9/30014
Arithmetic instructions: with variable precision
G06F 9/30065
To perform operations for flow control: loop control instructions; iterative instructions, e.g. LOOP, REPEAT
G06F 9/32
Arrangements for executing machine instructions, e.g. instruction decode: address formation of the next instruction, e.g. by incrementing the…