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US 8,046,399 B1Granted
Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module
AssigneeOracle America, Inc.
InventorsMurali K. Inaganti, Leonard D. Rarick
Life of this patent
Estimating the term…
Abstract
A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.
Claims14
A computer system comprising:
- a memory;
- and
- a processor coupled to said memory, said processor comprising:
- a fused-unfused floating point multiply-add (FMA) module, said fused-unfused FMA module for receiving a first multiply term, a second multiply term, and an addition term,
- wherein in response to said processor receiving a single unfused multiply-add opcode, said fused-unfused FMA module generates an unfused multiply-add rounding result,
- wherein in response to said processor receiving a single fused multiply-add opcode, said fused-unfused FMA module generates a fused multiply-add rounding result,
- wherein said unfused multiply-add rounding result is a rounded sum of said addition term with a rounded value of the product of said first multiply term and said second multiply term without obtaining the product of said first multiply term and said second multiply term,
- wherein in generating said unfused multiply-add rounding result, instead of generating said product of said first multiply term and said second multiply term, a first terminal partial product and a second terminal partial product are generated from said first multiply term and said second multiply term, and
- further wherein each said first terminal partial product and said second terminal partial product are truncated to produce, respectively, a truncated first terminal partial product and a truncated second terminal partial product, before being combined with said addition term.
6 more elements
A computer processor comprising:
- a fused-unfused floating point multiply-add (FMA) module, said fused-unfused FMA module for receiving a first multiply term, a second multiply term, and an addition term,
- wherein in response to said processor receiving a single unfused multiply-add opcode, said fused-unfused FMA module generates an unfused multiply-add rounding result,
- wherein in response to said processor receiving a single fused multiply-add opcode, said fused-unfused FMA module generates a fused multiply-add rounding result,
- wherein said unfused multiply-add rounding result is a rounded sum of said addition term with a rounded value of the product of said first multiply term and said second multiply term without obtaining the product of said first multiply term and said second multiply term,
- wherein in generating said unfused multiply-add rounding result, instead of generating said product of said first multiply term and said second multiply term, a first terminal partial product and a second terminal partial product are generated from said first multiply term and said second multiply term, and
- further wherein each said first terminal partial product and said second terminal partial product are truncated to produce respectively a truncated first terminal partial product and a truncated second terminal partial product before being combined with said addition term.
3 more elements
A computer system comprising:
- a memory;
- and
- a processor coupled to said memory, said processor comprising:
- a fused-unfused floating point multiply-add (FMA) module, said fused-unfused FMA module, said fused-unfused FMA module comprising:
- means for receiving a first multiply term, a second multiply term, and an addition term;
- and
- means for generating an unfused multiply-add rounding result of said first multiply term, said second multiply term, and said addition term, when in an unfused multiply-add rounding mode, and for generating a fused multiply-add result of said first multiply term, said second multiply term and said addition term, when in a fused multiply-add rounding mode,
- wherein said unfused multiply-add rounding result is a rounded sum of said addition term with a rounded value of the product of said first multiply term and said second multiply term without obtaining the product of said first multiply term and said second multiply term,
- wherein in generating said unfused multiply-add rounding result, instead of generating said product of said first multiply term and said second multiply term, a first terminal partial product and a second terminal partial product are generated from said first multiply term and said second multiply term, and
- further wherein each said first terminal partial product and said second terminal partial product are truncated to produce, respectively, a truncated first terminal partial product and a truncated second terminal partial product, before being combined with said addition term.
7 more elements
Dependencies are inferred from the claim text.