System of efficiently implementing secure hash algorithm (SHA-1) in digital hardware that accomplishes optimal computation speed using minimal hardware resources

A system of implementing the secure hash algorithm (SHA-1) for completing an 81-step SHA-1 computation in exactly 81 clock cycles, comprising:

• SHA-1 Logic Core;
• a quad-channel output memory (QCOM) having one data input channel and multiple data output channels for simultaneously retrieving multiple data elements from different memory locations referenced by an address value;
• a first synchronous registers set and a second synchronous registers set for storing the required computation values in the 81-step SHA-1 computation, wherein the second synchronous registers set is used to store the beginning value and the end value of a 160-bit hash value, and the first synchronous registers set is used to buffer intermediate computation values of the 160-bit hash value during the 81-step SHA-1 computation;
• a combination of asynchronous circuits for performing the logic and mathematic operations of each step of the 81-step SHA-1 computation on stored parameters within one single clock cycle;
• a counter circuit;
• a decoder/encoder circuit and a register used together with the counter circuit for performing tracking, counting, and controlling the 81-step SHA-1 computation;
• and
• a central control unit (CCU) for controlling internal units that perform the 81-step SHA-1computation and allowing an external system to access the 81-step SHA-1 computation;
• wherein the quad-output-channel memory comprises:
• an address decoder decoding a 4-bit address signal and a write-enable signal to create a 16-bit word-line-write signal;
• a 16×32-bit memory array with sixteen 32-bit words all connected to 32-bit input data-lines, a 16-bit word-line-write input connected to the output of the address decoder and the clock input connected to a clock signal;
• a first 32-bit sixteen-input multiplexer, a second 32-bit sixteen-input multiplexer, a third 32-bit sixteen-input multiplexer and a fourth 32-bit sixteen-input multiplexer, each multiplexing all sixteen 32-bit word outputs of the 16×32 memory array to make four 32-bit wide data output channels;
• a first 4-bit adder circuit with an input connected to the input address lines, the other input hardwired to an offset value of 13, and the 4-bit output connected to the 4-bit select input lines of the first 32-bit sixteen-input multiplexer to accomplish outputting the value of Wt-3;
• a second 4-bit adder circuit with an input connected to the input address lines, the other input hardwired to an offset value of 8, and the 4-bit output connected to the 4-bit select input lines of the second 32-bit sixteen-input multiplexer to accomplish outputting the value of Wt-8;
• and
• a third 4-bit adder circuit with an input connected to the input address lines, the other input hardwired to an offset value of 2, and the 4-bit output connected to the 4-bit select input lines of the third 32-bit sixteen-input multiplexer to accomplish outputting the value of Wt-14;
• wherein
• there are 4-bit address lines connected directly to the 4-bit select input lines of the fourth 32-bit sixteen-input multiplexer to accomplish outputting the values of Wt-16 and dout used by the SHA-1 Logic Core during counter t=0 to counter t=15 (step T=1 to step T=16).

A system of implementing the secure hash algorithm (SHA-1) for completing an 81-step SHA-1 computation in exactly 81 clock cycles said system comprising:

• An addressable memory device having one data input channel and multiple data output channels;
• and a SHA-1 Logic Core coupled to both (i) the multiple data output channels for the memory device to receive necessary data for the 81 step SHA-1 computation and (ii) the data input channel of the memory device to return intermediate computation values during the 81-step SHA-1 computation to the memory device;
• wherein within one operating clock cycle of the memory device, the data output channels of the memory device simultaneously output different memory words from different memory locations in accordance with a single address value at an address input port of the memory device;
• and wherein said single address value is modified internally within said memory device to identify said different memory locations
• wherein the memory device further comprises:
• a memory array;
• a clock input port:
• an enable-write input for, when activated, enabling data from the data input channel to be written into the memory array at a memory location referenced by the address value received at the address input port, wherein the data is written from the data input channel into the memory array within said one operating clock cycle of the memory device;
• wherein the data output channels output simultaneously within said one operating clock cycle of the memory device, different memory words stored in the memory array at different locations referenced by different computed address values obtained by differently modifying the address value
• wherein the memory device further comprises multiple multiplexers each corresponding to one of the data output channels;
• the multiplexers being commonly coupled to all memory word outputs of the memory array;
• one of the multiplexers being configured to output a memory word stored at a memory location referenced directly by the address value at the address input port;
• and each of the remaining multiplexers being configured to output a different memory word stored at a different memory location referenced by the respective computed address value obtained by modifying the address value received at the address input port.