Interpolative all-digital phase locked loop
AssigneeTexas Instruments Incorporated
InventorsKhurram Waheed, Robert Bogdan Staszewski, John L. Wallberg, Sudheer K. Vemulapalli
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Abstract
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
Claims27
A digital system comprising a phase locked loop (PLL), wherein the PLL comprises:
- a frequency reference input for receiving a reference clock;
- a controllable oscillator for generating a radio frequency (RF) clock;
- a phase detection circuit operational on said reference clock for providing digital phase error samples;
- an interpolator coupled to said phase detection circuit for performing a sample rate conversion of the phase error samples between said reference clock and a clock derived from said RF clock;
- and
- a loop filter circuit operable on said derived clock being coupled between the interpolator and the controllable oscillator, the loop filter operable to provide filtered frequency tuning adjustment to the controllable oscillator.
A digital system comprising a transmitter, wherein the transmitter comprises:
- a frequency reference input for receiving a reference clock;
- a phase locked loop (PLL) comprising:
- a controllable oscillator for generating a radio frequency (RF) clock;
- a phase detection circuit operational on said reference clock for providing phase error samples;
- and
- an interpolator coupled to said phase detection circuit for performing a sample rate conversion of said phase error samples between said reference clock and a clock derived from said RF clock;
- and
- a data modulating input for providing data deviation commands coupled to the PLL, the data deviation commands operable to adjust operation of the PLL:
- and
- a second interpolator coupled to receive said data deviation commands;
- said second interpolator operable to provide interpolated data deviation commands to said phase detector circuit.
A cellular telephone comprising:
- a reference frequency generator for forming a reference clock;
- a transmitter connected to receive the reference clock, comprising:
- a phase locked loop (PLL), wherein the PLL comprises:
- a controllable oscillator for generating a radio frequency (RF) clock;
- a phase detection circuit operational on said reference clock for providing digital phase error samples;
- an interpolator coupled to said phase detection circuit for performing a sample rate conversion of said phase error samples between said reference clock and a clock derived from said RF clock;
- and
- a loop filter circuit operable on said derived clock being coupled between the interpolator and the controllable oscillator, the loop filter operable to provide filtered frequency tuning adjustment to the controllable oscillator.
A method for transmitting, comprising:
- generating a reference clock signal;
- generating an adjustable radio frequency (RF) clock signal;
- detecting phase error between the reference clock signal and the RF clock signal and providing phase error samples synchronous with said reference clock;
- performing a sample rate conversion of the phase error samples between the reference clock and a clock derived from said RF clock by interpolation of the phase error samples;
- filtering the interpolated phase error samples with reference to the derived RF clock;
- and
- adjusting the RF clock signal in response to the filtered interpolated phase error samples.
A method for transmitting, comprising:
- generating a reference clock signal;
- generating an adjustable radio frequency (RF) clock signal;
- detecting phase error between the reference clock signal and the RF clock signal and providing phase error samples synchronous with said reference clock;
- performing a sample rate conversion of the phase error samples between the reference clock and a clock derived from said RF clock by interpolation of the phase error samples;
- adjusting the frequency of the RF signal in response to data deviation commands;
- updating the data deviation commands synchronously to a clock signal derived from the RF clock;
- performing a sample rate conversion of the updated data deviation commands between the RF derived clock and the reference clock by interpolation of the data deviation commands, and
- using the interpolated data deviation commands in the process of detecting phase error between the reference clock signal and the RF clock signal.
Dependencies are inferred from the claim text.