Digital phase-locked loop operating based on fractional input and output phases

A method comprising:

• determining a phase error based only on a fractional portion of an input phase and a fractional portion of an output phase for an oscillator signal from an oscillator;
• and
• generating a control signal for the oscillator based on the phase error, wherein the fractional portion of the input phase and the fractional portion of the output phase each has a range of one cycle of the oscillator signal.

An apparatus comprising:

• means for determining a phase error based only on a fractional portion of an input phase and a fractional portion of an output phase for an oscillator signal from an oscillator;
• and
• means for generating a control signal for the oscillator based on the phase error, wherein the fractional portion of the input phase and the fractional portion of the output phase each has a range of one cycle of the oscillator signal.

An apparatus comprising:

• an oscillator configured to generate an oscillator signal;
• and
• a digital phase-locked loop (DPLL) configured to receive the oscillator signal from the oscillator and a reference signal and to generate a control signal for the oscillator, the DPLL comprising a synthesized accumulator configured to determine a coarse output phase by keeping track of a number of cycles of the oscillator signal, the synthesized accumulator being updated based on the reference signal having a frequency lower than a frequency of the oscillator signal.