Clock data recovery device
AssigneeThine Electronics, Inc.
InventorSeiichi Ozawa
Life of this patent
Estimating the term…
Abstract
A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n−1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n−1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.
Claims7
A clock/data recovery device for recovering a clock signal and data based on an input digital signal, comprising:
- a sampler for receiving an input of a clock signal CK and a clock signal CKX, which have a same cycle T(n), and also receiving the input digital signal, setting a signal to which an offset (−Voff) has been applied to the input digital signal as a first signal, setting a signal to which an offset (+Voff) has been applied to the input digital signal as a second signal, and in each nth period T(n) of the same cycle, sampling, holding and outputting a digital value DA(n) of the first signal and a digital value DB(n) of the second signal at a time tc indicated by the clock signal CK, and sampling, holding and outputting a digital value DXA(n) of the first signal and a digital value DXB(n) of the second signal at a time tx indicated by the clock signal CKX (where “tc<tx” and n is an integer);
- a detector for, in each period T(n), receiving an input of the digital value DA(n), digital value DB(n), digital value DXA(n) and digital value DXB(n) outputted from the sampler, determining a digital value D(n) and a digital value DX(n−1) by setting “D(n)=DA(n)” and “DX(n−1)=DXA(n−1)” in a case where a value D(n−1) is HIGH level and setting “D(n)=DB(n)” and “DX(n−1) =DXB(n−1)” in a case where the digital value D(n−1) is LOW level, and detecting a phase relationship between the clock signal CK and the input digital signal based on the digital value D(n−1), digital value DX(n−1) and digital value D(n);
- an offset determination part for, in each period T(n), receiving an input of the digital value D(n) and digital value DX(n) determined by the detector, and determining an amount of an offset (±Voff) added in the sampler such that a time indicated by the clock signal CKX constitutes the center of a transition time distribution of a value of the first signal in a case where the digital value D(n−1) is HIGH level, and a time indicated by the clock signal CKX constitutes the center of a transition time distribution of a value of the second signal in a case where the digital value D(n−1) is LOW level;
- and
- a clock output part for adjusting either the cycle T(n) or a phase based on the phase relationship detected by the detector such that a phase difference between the clock signal CK and the input digital signal decreases, and outputting to the sampler the clock signal CK and the clock signal CKX that satisfy the relationship “tx−tc=T/2”.
Dependencies are inferred from the claim text.