Low power, high speed receiver circuit for use in a semiconductor integrated circuit

A receiver circuit comprising:

• a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of threshold detection levels, and transmits a first output signal;
• a second phase transmission unit coupled with the first phase transmission unit, the second phase transmission unit synchronized with a second clock and configured to detect the input data according to an output of a first discharging control unit, and transmits a second output signal;
• and
• the first discharging control unit coupled with the second phase transmission unit, the discharge control unit configured to control the second phase transmission unit in response to the first output signal and adjust the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined.